[SOLVED] Verilog error, Please help

Embedding signal declarations within the functional code instead of only after the module port declarations is a bad coding practice IMO.

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abimann said:

I want to say thank you for guys which is always help me and others, and spent their time, based on this our world going to be better.

I am know nothing in Verilog, here should be problem related to FPGA chip, because when i change to Virtex-4 from Spartan-6, there always error not declared :

Code:

ERROR:HDLCompilers:28 - "TestCapture.v" line 26 'real_data' has not been declared
ERROR:HDLCompilers:28 - "TestCapture.v" line 27 'pixel_fg' has not been declared

But when I change to Spartan-6 thats ok. Could someone tell me what to do ?
This project taken from https://github.com/zafartahirov/background_subtract_XILINX

Code:

`timescale 1ns / 1ps
`define IDLE					0
`define WAIT_4_NEW_FRAME	1
`define RECORD_IMAGE			2
`define PROCESS_IMAGE		3

module test_buffer(
	input [4:0] pixel_in,
	output [4:0] pixel_out,

	input [30:0] hCounter_in,
	input [30:0] vCounter_in,

	input clk
	);

	wire [4:0] pixel_temp;
	wire blank_bg, blank_fg, blank_real;

	assign blank_bg 	= (hCounter_in >= 640 | vCounter_in >= 480);
	assign blank_real = 	hCounter_in < 170 | hCounter_in >= 330 | vCounter_in >= 140;
	assign blank_fg	=	hCounter_in < 340 | hCounter_in >= 500 | vCounter_in >= 140;
	

assign pixel_out =  ( {16{~blank_bg}} & pixel_temp ) |
                    ( {5{~blank_real}} & real_data ) |
                    ( {5{~blank_fg}} & {5{pixel_fg}}   );
/////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////

reg [14:0] counter_address, counter_address_real, counter_address_fg;
reg wea = 1;
reg [12:0] proc_d;	// processed data from BRAM
wire [14:0] addr_write = (counter_address==0)? 22399: counter_address-2;	// computes the address of the BRAM

reg [12:0]temp_bg;	// computed background (going to the BRAM)

reg [4:0] temp_real;	// input from the camera
reg [4:0] real_data;	// output of the camera feed
reg temp_fg;				// the difference (goes to the BRAM)

reg pixel_fg;	// the difference for foreground detection
wire [4:0] difference;

assign pixel_temp={temp_bg[11:7]};	// background output pixel

assign difference[4:0] = (temp_real[4:0] > pixel_temp[4:0]) ?
											(temp_real[4:0] - pixel_temp[4:0]) :
											(pixel_temp[4:0] - temp_real[4:0]);

always @(posedge clk) begin
	// compute the current address for the BG detection
	// as well as real feed
	if (~blank_bg) counter_address <= counter_address+1;
	if (counter_address >= 22399) counter_address <= 0;

	if (~blank_real) counter_address_real <= counter_address_real+1;
	if (counter_address_real >= 22399) counter_address_real <= 0;

	if (~blank_fg) counter_address_fg <= counter_address_fg+1;
	if (counter_address_fg >= 22399) counter_address_fg <= 0;

end

always @ (posedge clk) begin
	if (~blank_bg) begin
		temp_bg[12:0] = 	proc_d[12:0] 	- proc_d[12:7] 	+ pixel_in[4:0];

		temp_real = pixel_in;
		temp_fg =(difference[4:0] > 5);
	end
end

 //stores computed background
buffer_data1  buffer_data (
    .clka(clk),
    .wea(wea),
    .addra(addr_write),
    .dina(temp_bg),
    .clkb(clk),
    .addrb(counter_address),
    .doutb(proc_d)
  );

// stores real feed
bram_current_frame buffer_data_real(
	 .clka(clk),
    .wea(wea),
    .addra(addr_write),
    .dina(temp_real),
    .clkb(clk),
    .addrb(counter_address_real),
    .doutb(real_data)
);

// stores the difference frame
bram_fg buffer_data_fg(
	 .clka(clk),
    .wea(wea),
    .addra(addr_write),
    .dina(temp_fg),
    .clkb(clk),
    .addrb(counter_address_fg),
    .doutb(pixel_fg)
);
endmodule

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sreevenkjan said:

how is it possible that you could pull it off with Spartan-6? did you check the settings? as ads-ee suggested you can declare the variables earlier and also move the "assign" blocks down

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abimann said:

Dear all , i made screenshot , brams are made for Virtex-4 not for Spartan6.View attachment 145575 this exactly based on fpga chip error

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sreevenkjan said:

if you have a look at my post #4, I suggested to check the settings, in this case I would suggest you to choose appropriate FPGA and then compile the project. you cannot have 1 device and compile the project meant to be for another device. It does not work like that.

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abimann said:

ads-ee, I use new directory create file and only copy sources, BRAM ips are generated for Virtex-4 only .. when i use wire instead reg it also error...

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