timing on design compiler

Hi everyone.

From what I know, critical path is the longest path between two flip-flops in a design.
However, based on the timing report, the critical is not between two flip-flops.
Can someone please explain to me why is that?
Does ACIS and FPGAs have different critical path definition?

****************************************
Report : timing
-path full
-delay max
-max_paths 1
-sort_by group
Design : ProcessingElement
Version: J-2014.09-SP2
Date : Mon Feb 26 08:42:27 2018
****************************************

Operating Conditions: cb13fs120_tsmc_max Library: cb13fs120_tsmc_max
Wire Load Model Mode: enclosed

Startpoint: QC[2] (input port clocked by Clk)
Endpoint: LeftOut[0] (output port clocked by Clk)
Path Group: Clk
Path Type: max

Des/Clust/Port Wire Load Model Library
------------------------------------------------
ProcessingElement 8000 cb13fs120_tsmc_max

Point Incr Path
--------------------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.30 0.30
input external delay 2.00 2.30 r
QC[2] (in) 0.00 2.30 r
U1/Z (bufbd1) 0.09 2.39 r
LUT/U5/ZN (inv0d1) 0.74 3.13 f
Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_1/CO (ad01d0)
0.50 3.63 f
Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_2/CO (ad01d0)
0.28 3.91 f
Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_3/CO (ad01d0)
0.28 4.18 f
Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_4/CO (ad01d0)
0.28 4.46 f
Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_5/CO (ad01d0)
0.28 4.73 f
Algorithm/Iyij/Mij1/add_0_root_add_0_root_add_17_2/U1_6/S (ad01d0)
0.34 5.07 r
Algorithm/Iyij/Mij1/U4/Z (an02d1) 0.16 5.23 r
Algorithm/Iyij/LeftComp/U38/ZN (oai221d1) 0.36 5.59 f
Algorithm/Iyij/LeftComp/U40/Z (aoim22d1) 0.29 5.88 r
Algorithm/Iyij/LeftComp/U29/Z (aor21d1) 0.28 6.16 r
Algorithm/Iyij/LeftComp/U3/ZN (inv0d1) 0.28 6.44 f
Algorithm/Iyij/LeftComp/U13/Z (aor22d1) 0.63 7.08 f
LeftOut[0] (out) 0.00 7.08 f
data arrival time 7.08

clock Clk (rise edge) 40.00 40.00
clock network delay (ideal) 0.30 40.30
output external delay -1.65 38.65
data required time 38.65
--------------------------------------------------------------------------
data required time 38.65
data arrival time -7.08
--------------------------------------------------------------------------
slack (MET) 31.57

Critical path can be understood as the hardest path for Design Compiler to make it MET.
It has no reason to exist only on FlipFlop to FlipFlop path.

Critical path can exist on any VALID path which has been constrained,
including INPUT --> REG, REG --> REG, REG --> OUTPUT, INTPUT --> OUTPUT