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[SOLVED] I2c bus specification

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RAHUL_KUMAR

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1st question: "The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pf ". This is written in the Philips I2C bus specification .
i want to know how number of ICs is dependent of bus capacitance ? I am not getting any visualization here.


2nd question: "On chip filtering ejects spikes on the bus data line to preserve data integrity in I2C bus ". Can u plz elaborate it too if possible.
 

When you connect more ICs to the same bus each IC introduces its own parasitic capacitance to the bus. More devices you have on the bus more parasitic capacitance you have. For your 2nd question I guess I need to see that in the context that its used.
 
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    RAHUL_KUMAR

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Hi,

1)
The more devices you connect the more capacitive bus load you generate. Each piece of wire generate capacitoance and ech IC input generates capacitance (datasheet should show).

2)
a spike may cause an additional pulse at the clock line or erroneous logic state at the data line. A low pass filter may reduce the effects of spikes and thus increases data and clock integrity.

Klaus
 

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How does spikes play role in loosing data integrity ......this question is in context of below line
(On chip filtering rejects spikes on the bus data line to preserve data integrity) this line is mentioned on Philips I2C data bus specification sheet.
 

Not quite sure what your question is, but if you have a spike on your data line it could possible cause a "zero" bit to be interpreted as a "one", or vice versa. The data sheet is telling you that there is filtering applied to help eliminate spikes.
 

Hi,

a spike on the clock line may be mis-interpreted as a true clock pulse.

If now one bit per clock is transmitted, then one bit (and all folowing) may be not be interpreted correctly.

Klaus
 

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