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How set_disable_timing is different from set_false_path

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sathish patkutwar

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Hi,

I have some confusion between set_false_path and set_disable_timing.

How different are these two from one another.

Can't we achieve set_disable_timing with set_false_path??
 

1. Target objects:
- set_disable_timing: applied on timing arcs. E.g input to output of a AND cells.
- set_false_path: applied on timing paths.

2. Effects:
- set_disable_timing: the arc is set to inactive and invisible from any logic transition that will be used in timing calculation, or constant propagation.
- set_false_path: the path timing will be ignored from timing optimization and STA timing calculation of tools.
 
slutarius said:
1. Target objects:
- set_disable_timing: applied on timing arcs. E.g input to output of a AND cells.
- set_false_path: applied on timing paths.

2. Effects:
- set_disable_timing: the arc is set to inactive and invisible from any logic transition that will be used in timing calculation, or constant propagation.
- set_false_path: the path timing will be ignored from timing optimization and STA timing calculation of tools.
Click to expand...

Hi Thanks for the info.

I have few couple of questions on this.

1> Does the tool fixes timing DRV/DRC on the cells/nets which falls under set_false_path/set_disable_timing
2> does the logic propagates through false_path/disable_timing during GateLevelSimulation.

Thanks in advance,
Sathish Patkutwar
 
False paths and disable paths have no 'physical meaning' per se. it affects the optimization and timing analysis, but of course you still need to check DRC on them, and of course the logic still propagates in simulation.
 

sathish patkutwar said:
Hi Thanks for the info.

I have few couple of questions on this.

1> Does the tool fixes timing DRV/DRC on the cells/nets which falls under set_false_path/set_disable_timing
2> does the logic propagates through false_path/disable_timing during GateLevelSimulation.

Thanks in advance,
Sathish Patkutwar
Click to expand...

1> Please distingish the difference in Timing DRC and Physical DRC. false_path and disable_path should not effect to the PV DRC checker.
2> Please keep in mind that there are no false_path/disable_path command in Gate sim. So, no effect.
 

slutarius said:
1> Please distingish the difference in Timing DRC and Physical DRC.
Click to expand...

The terminology I have adopted is from Cadence. Timing-related violations are DRVs, while physical violations are DRCs. DRVs are fanout violations, max cap, max tran.
 

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