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When in a package or a chip, the signals are changing very fast, the inductances in the bondwires or inside the chip or at the device level will cause a change in the voltage as per V = L*di/dt. Hence your ground will actually vary rather than staying at zero potential. This will distort the quality of the signal.
This has become a very big issue due to the increased speeds. The slewing constraints have to be met. So, we put bypass capacitors between the supplies in order for the voltage spikes to reduce.
I hope that it helps......
Added after 2 minutes:
The reason why the term is called ground bounce is because the output voltage, when it is expected to fall to ground, does not actually do so. It starts falling but due to the voltage due to the current spikes, it bounces from the ground level.
Suppose you have 16-bit bus driver in one package. And it should drive very heavy capacitance load. Suppose you need to switch 15 of the outputs from 1 to 0 and one of them should be kept in low state (always 0 and is not switching).
If you will monitor this last output by oscilloscope you will see some positive spike on this output. If the spike amplitude will exceed threshold voltage of the receiver it will be considered as short positive pulse.
This spike is caused by package inductance (GND) and heavy capacitance load. At the very first time output current of each output pin have the max. value because all the output transistors operate in saturation region. And all this max. currents flowing trough GND inductance cause "grounde bounce".
Ground bounce, in a nutshell, is the ground voltage perturbation due to large currents moving in and out of I/Os. Circuits usually are tested for this kind of ground bounce using 0000_0000 FFFF_FFFF pattern. If circuit can take this pattern w/o problem, chances are that it will work fine with random data as well.
You can reference razavi's AIC book.
In short, it's the noise between analog and digital circuit. For example, the clock signal switching noise is directedly coupled by substrate to the analog part.
When in a package or a chip, the signals are changing very fast, the inductances in the bondwires or inside the chip or at the device level will cause a change in the voltage as per V = L*di/dt. Hence your ground will actually vary rather than staying at zero potential. This will distort the quality of the signal.
This has become a very big issue due to the increased speeds. The slewing constraints have to be met. So, we put bypass capacitors between the supplies in order for the voltage spikes to reduce.
I hope that it helps......
Added after 2 minutes:
The reason why the term is called ground bounce is because the output voltage, when it is expected to fall to ground, does not actually do so. It starts falling but due to the voltage due to the current spikes, it bounces from the ground level.
Just want to know V= L*di/dt will be generated across the inductor?
My doubt:
I am considering one circuit of a CMOS inverter with NMOS connected to an inductor before it connects to a ground.
When the PMOS is on, Vout= 1 (say 5 volt = '1' and 2 volt = '0')
and in when the NMOS is on PMOS is off. At that time Vout will start to drain out through NMOS, consequently current will flow through inductor.
say after time 't' the voltage across the inductor is V= L*di/dt
At one time this will occur
Vout = V and both are less than 5volt.
Beyond that time a time will come when V will be slightly greater than Vout. At that time NMOS will swap it's source and drain. That means so far what was drain, will now be source. And V will start to drain through NMOS and it will add to Vout.
This process will continue till NMOS is ON. And so Vout will never go to ground. This is ground bounce.
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