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I2C delay between SCL and SDA

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manush30

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Hi everyone,

I try to write a code with 4 lines of I2C.
I want to make delay for 1us and measure it through oscilloscope.
( SCL1 & SDA1 and after the delay SCL2 & SDA2 and compare them)

i have I2C master and a 8 GPIO to measure it with a scope.
I have 50M CLK on the board.

I try to do it like this:

Code: 
PROCESS(SCL_OE, SCL)
  BEGIN
IF (DELAY <= 50) THEN
   IF SCL_OE='0' THEN
		SCL <= 'Z';
	ELSE
		SCL <= '0';
	END IF;
        DELAY<= DELAY +1;
ELSE 
    IF SCL_OE='0' THEN
		SCL_O <= 'Z';
	ELSE
		SCL_O <= '0';
	END IF;
        DELAY<=0;
END IF;
the same to the SDA line.

IT DOESN'T WORKKKK:???:
 

The process isn't being clocked by your 50MHZ clock. You are "clocking" it with changes on SCL_OE and SCL.

Also, the check of DELAY should be 49, not 50. Remember that you are starting at 0 and not 1.

***Added
I just noticed that while you have SCL in the sensitivity list, you are assigning it values, so it should not be in the list.
 
Last edited:

Thanks a lot bking.

Still it doesn't work..
I've changed the process but still i did not see the delay :bang:
 

You probably overlooked the words "isn't being clocked". Sensitivity lists are simply ignore for synthesis. There must be a condition like rising_edge(clk) to actually count clock cycles.
 

Hi all and Sorry about the ignition (i've been sick 8 days:sad:)

The problem was with the GPIO driver i had in my board.
it doesn't recommended for I2C lines( https://www.nxp.com/docs/en/data-sheet/NTB0104.pdf page 19)

I've changed my system and try to delay only the SDA.

I've work with I2C master aadvark total phase (https://www.totalphase.com/products/aardvark-i2cspi/).
I need to write a code that delay the SDA signal for 1us.
I have the CPLD board and the slave at the end of the system (addr 5F)

I've tried to write the code but I still have some issues:???:

When i write to the slave, how i recognize the SDA push to zero and also how I delay the data for 1us?
- the SDA_in need to be with pull-up so when the master pull to zero (writing) i can recognize the change if i will compare it to my system CLK?
will it work?
- And then delay it for 1us and send it to the slave:
SDA_OUT <= SDA_IN;

One more thing, the two lines must to be INOUT mode and tri states signals.

problema!

Can any one help me with this pls:roll:
 

If you only delay the data then you will likely have no clock to shift it out with, assuming you are using SCL. SCL is not a constant clock.

Can you explain why you need to delay the data? Maybe there is a better way of doing this than what you are trying now.
 
Hi,

This device is not recommended for new designs.

It has built in standard I2C interface, no need for doing handstands on SCL.
I wonder what's the real problem.

Klaus
 
Buffering the bidirectional SDA signal in a PLD requires partial I2C protocol decoding to determine the data direction. Dedicated I2C buffer ICs are using special analog features that are not available in PLD GPIO.
 

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