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VHDL Constant Declaration

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hareeshP

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Hi,
i want to declare a constant 5 bit value in vhdl and i want to access that constant value throughout the program.
 

constant x: std_logic_vector ( 4 downto 0 ) := "10011" ; -- declare this between "architecture" and "begin"
 
thanks for your valuable comments,
but when i declare it as a package like,
/////////////////////////////////
package package_name is
constant name: type ;
end package_name;
////////////////////////////////
do i need anything else to declare for the package declaration?
 

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package vhdl_pkg is
. 
constant x: std_logic_vector ( 4 downto 0 ) := "10011" ; 
.
end vhdl_pkg;

-- If package body is required
package body vhdl_pkg is
.
.
.
end package body;

In places where you need to use the package put this before the entity declaration: use work.vhdl_pkg.all;
 

Follow-up question,

Is it possible to declare 2 (or more) constants of the same name in different packages ?
And be able to access both (somewhat like structures in C) ?

if package_1.x = some_value ...
if package_2.x = some_value ...
 

You can do this with libraries if you are willing to deal with the "work" library weirdness. Not sure about packages as I've never had a need for this.
 
shaiko said:
Follow-up question,

Is it possible to declare 2 (or more) constants of the same name in different packages ?
And be able to access both (somewhat like structures in C) ?

if package_1.x = some_value ...
if package_2.x = some_value ...
Click to expand...

Yes. In any name conflict situation, you must use the full path to use then item, otherwise neither are visible. The common situation is when people include both std_logic_arith and numeric_std in the same file. Apart from deleting std_logic_arith, they can work around it by using the full path:

Code: 
signal a : ieee.numeric_sd.unsigned(7 downto 0);
signal b : ieee.std_logic_arith.unsigned(7 downto 0);

Similarly, the common quoted "you cant use std_logic_unsigned and std_logic_signed" in the same file is also not technically true. You can just provide the path to the "+" function you wanted:

Code: 
my_output0 <= a ieee.std_logic_unsigned."+" b;
my_output2 <= a ieee.std_logic_signed."+" b;

- - - Updated - - -

vGoodtimes said:
You can do this with libraries if you are willing to deal with the "work" library weirdness. Not sure about packages as I've never had a need for this.
Click to expand...

Its not really weird, work is just the default library, and acts like any other library. Though many people use it as a local library, its not true. What people often do is compile everything into work. The from another project, map "my_other_library" to the existing work library. Mapping is a tool defined construct, not a VHDL one.
 
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    shaiko

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when declare like this it is showing an error
'object "std_logic" is used but not declared '
 

no...i have written the library.
but still it is showing the error.
////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_pkg.all; // is this correct??
package vhdl_pkg is
constant CHIPID2: std_logic_vector(4 downto 0):= "00001";
end vhdl_pkg;
entity test is
port( clk: in std_logic
------------
//////////////
 

If you put the package and entity definition in one file, you still need separate library clauses for both design units. The library reference in your code works for the package only. Should look like below

Code VHDL - [expand]
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library ieee;
 use ieee.std_logic_1164.all;
 
 package vhdl_pkg is
 constant CHIPID2: std_logic_vector(4 downto 0):= "00001";
 end vhdl_pkg;
 
library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
library work;
 use work.vhdl_pkg.all;
 
 entity test; -- .....
 
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