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monostable multivibrator

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nihilo

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hello All

I need to understand how the circuit works in order to replace this obsolete chip.

It's clear how the circuit works on the left monostable multivibrator circuit. I have a fix high level input (1B). When 1A goes low the Q output triggers.

Now the question is for the right circuit, I have 2A and 2B input connected to a bunch of resistors and a transistor. I am not sure how it works, I think input 2A is kept low all the time.
I believe F_1 is an input.
Can anyone help me out?


MM74C221
https://media.digikey.com/pdf/Data Sheets/Fairchild PDFs/MM74C221.pdf
 

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  • Mult_mono.JPG
    Mult_mono.JPG
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Hi,

Possibly: 2B is high, until Q6 turns on and draws the voltage to ground which held 2B high. 2A is low (because it's input voltage is high) when Q6 is off. it looks like R45 charges C3 and maybe C23, until Q6 goes high and drains the capacitors? 2A doesn't look as though it is low all the time as it is connected to 12V via R26. If it's high going into the internal inverter all the time then it will be low at the output fo the internal inverter, I don't see how that would be useful because 2A and 2B feed an AND gate, so both would need to be high (internally) at the same time at at least some point for the AND gate to go high at some point. If it's always low going into the 2A inverter, and therefore internally high at the inverter's output, then that's a different story.

I would have thought F_1 were an output, but it could equally be something entirely different without being able to see what is connected to it.

I'm probably wrong about several parts of the interpretation above.
 

The chip looks like a 74LS221 (dual monostable). Look at the datasheet here.
 


d123 said:
Hi,

Possibly: 2B is high, until Q6 turns on and draws the voltage to ground which held 2B high. 2A is low (because it's input voltage is high) when Q6 is off. it looks like R45 charges C3 and maybe C23, until Q6 goes high and drains the capacitors? 2A doesn't look as though it is low all the time as it is connected to 12V via R26. If it's high going into the internal inverter all the time then it will be low at the output fo the internal inverter, I don't see how that would be useful because 2A and 2B feed an AND gate, so both would need to be high (internally) at the same time at at least some point for the AND gate to go high at some point. If it's always low going into the 2A inverter, and therefore internally high at the inverter's output, then that's a different story.

I would have thought F_1 were an output, but it could equally be something entirely different without being able to see what is connected to it.

I'm probably wrong about several parts of the interpretation above.
Click to expand...
You are right, It makes more sense. If we look at the logic table, B is kept HIGH, and when a transition to LOW occurs on A the output triggers. This is how it is supposed to work.
So the capacitor C3 does the job by turning on/off the transistor therefore it changes the input A level. Seems so.

I have not idea whether F_1 is an output or input, it goes to a connector, that is all I know.

Thanks a lot.
 

The circuit looks wrong, is R19 in the right place?
,
the base of the transistor will hold 2A input at .6V ?
If you want a low, then ground the pin.

Is the circuit reversed engineered?
My guess is R19 is suppose to be between the base and the pull up R26.
Also I think Vcc is missing from R31|R44
 

RobertFalbo said:
The circuit looks wrong, is R19 in the right place?
,
the base of the transistor will hold 2A input at .6V ?
If you want a low, then ground the pin.

Is the circuit reversed engineered?
My guess is R19 is suppose to be between the base and the pull up R26.
Also I think Vcc is missing from R31|R44
Click to expand...

Yeah, I have to reverse engineering this board.
I double checked again and actually the circuit is a bit different, here the scheme.

Mult_mono_updated1.JPG
 

nihilo said:
Yeah, I have to reverse engineering this board.
I double checked again and actually the circuit is a bit different, here the scheme.

View attachment 139263
Click to expand...

Are you sure that Q6 is a NPN and not a FET?
I bet base / collector is swapped.


Having the input pin 9 tied to a base of a NPN with the emitter to ground bothers me.

R45 and C3 are a RC timing about 50 mS.
R19 confuses me. The only reason I could see is to reduce the effect of the gate currrent on the RC timing.
 
Last edited:

scheme.jpgtransNPN.jpg

As you can see in the pic the transistor is a ztx 3704 which is a NpN general purpose transistor.
I know it looks strange but this is how it's wired.
I attached the scheme so you can check it yourself.

Thank you for your help!

- - - Updated - - -

scheme.jpg

Sorry this pic has the correct frame around U1.
 

Without voltage supply to F_1 node, the transistor won't work at all.
 
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    nihilo

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Yes I agree, probably F_1 is a Supply Voltage coming from the connector. Thx
 

Seems like a pretty screwy circuit. The NPN Vbe ought to
never let 2A go logic-high, so why not just ground it? The
network on 2B, I don't even have a guess as to what that
could be trying to achieve (other than maybe some kind of
power-on reset pulse?).
 

That transistor is a E B C, you swapped base and collector in your reverse engineering.

- - - Updated - - -
 
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    nihilo

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Hello Robert

Do you have link of the datasheet? I need to figure it out if they are inverted.
Thank you!

Edit:

found the pin out, yes you are right I was looking at the 2n3704. So the circuit now it makes more sense.
 
Last edited:

Tmart_Updated_22th_giu.JPG

Sorry people for messing up.
Here the correct schema.

Now back to the initial question. Can we say that 2A (pin 9) is kept high and it waits for 2B to go low to trigger the output (1Q) ?
Can you guess if F_1 is an input or output?

Thank you again!

RobertFalbo said:
That transistor is a E B C, you swapped base and collector in your reverse engineering.

- - - Updated - - -
Click to expand...

looking at the transistor I thought ztx was the manufacturer and 3704 the part number. Typing that separately on google the only component it finds is the 2N3704 so I thought, that is.
This one has inverted collector and base.
But if you type ztx3704 you can find very obsolete links of the pinout but no datasheet.
So it is my bad I didn't pay much attention, I hope this mistake was reasonable.

- - - Updated - - -

nihilo said:
Tmart_Updated_22th_giu.JPG

Sorry people for messing up.
Here the correct schema.

Now back to the initial question. Can we say that 2A (pin 9) is kept high and it waits for 2B to go low to trigger the output (1Q) ?
Can you guess if F_1 is an input or output?

Thank you again!



looking at the transistor I thought ztx was the manufacturer and 3704 the part number. Typing that separately on google the only component it finds is the 2N3704 so I thought, that is.
This one has inverted collector and base.
But if you type ztx3704 you can find very obsolete links of the pinout but no datasheet.
So it is my bad I didn't pay much attention, I hope this mistake was reasonable.
Click to expand...

Small correction.
Tmart_Updated_22th_giu.JPG
 

The circuit issues a rest pulse on power up after a short period, R45 C3 is the timing for that.
There is an external reset by putting a high on F1.

R53 and C2 dictate how long the rest pulse is.
 

RobertFalbo said:
The circuit issues a rest pulse on power up after a short period, R45 C3 is the timing for that.
There is an external reset by putting a high on F1.

R53 and C2 dictate how long the rest pulse is.
Click to expand...

Sorry for the late replay. Thank you anyways.

By putting a high on F1, doesn't it mess up with the C3 capacitor? I see the reset is on the negative side of the capacitor.

Is not clear how the 2 inputs work.
2A remains high as long as the transistor remains open.
2A goes low when the transistor closes.

As for 2B goes, I see it is connected to the capacitor which charges up to 12V. I don't see how 2B input changes.
Could anyone help me understand?
 

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