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Declaring multidimensional array problem in Modelsim

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manik045

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Hello

I can not declare a multidimensional array in modelsim for systemverilog. Here's the code

Code: 
module TwoD_Array ();
  
 bit [7:0] array[1:2][1:4];
   
  initial begin
    
 /*   array [0][0]=8'd50;
    array [0][1]=8'd60;
    array [1][0]=8'd70;
    array [1][1]=8'd90; */

    
    //$display ("array [0][0]=%d", array[2]);
    
    end 
endmodule


When i am going to compile it gives me the following error message.

** Error: C:/altera/12.1/modelsim_ase/multiple array.bak(3): near "[": syntax error, unexpected '[', expecting IDENTIFIER or TYPE_IDENTIFIER
Click to expand...

I can not figure it out. Where is the problem of declaring the array here.


Please help me to figure it out.
 

Maybe you need to repost the problem. The [0][0] indecies don't even exist in the declaration of array?

Also you are trying to display an entire row of the array with the array[2] with a %d. Maybe that's something new in SV that I've never heard of before?
 

I suspect you are compiling the wrong file. "multiple array.bak" makes me think that this is a backup file and that you are editing "multiple array.sv" .

Otherwise, there doesn't seem to be anything other than the declaration of the array. Everything else is commented out leaving an empty initial block.
 

I see
expecting IDENTIFIER or TYPE_IDENTIFIER"
Click to expand...
and I immediately think,

Where is wire or reg.
 

    V

    Points: 2
    Helpful Answer Positive Rating
The problem is with name of the file. It needs to have a *.sv extension to be recognized as SystemVerilog. "bit" is not a legal keyword in Verilog.
 

Nice. And the error is on the bracket as "bit" might be the name of a component or task defined in another file. One day we'll get clang-style error messages.
 

touching on #5

SystemVerilog
**broken link removed**
Verilog
**broken link removed**

Turns out there are quite a few deviations.

Anyone got any inclination into when we will get another Verilog/sv/vhdl standard released? It's about time they merged them into one super language/ have more commonality with keywords.
 

    V

    Points: 2
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Verilog is now a subset of system verilog as of sv2005.

Vhdl is getting another release this year. Look forward to support in 2025.
 

TrickyDicky said:
Verilog is now a subset of system verilog as of sv2005.
Click to expand...

I read somewhere SV was supposed to be released as Verilog 2005 not as SV2005. The Acellera additions to the language got released with the wrong name. Now a lot of people think they are different languages, they aren't. All of Verilog exists in SV (or at least everything I use).

Maybe you'll see 10% support of new features by 2025, and then only the stuff you don't care about ;-)
 

They are slowly merging -- VHDL got the easy std_logic_vector to boolean conversion syntax. Verilog got structs (and more). It technically got functions on unconstrained vectors, but not in an obvious way.

However, people don't use existing synthesizable features. Vendors don't implement synthesis support for synthesizable features. And both languages are simulation-first with synthesis as a happy accident.

Add to this existing developers who actually like the old ways and there is little reason to add anything to the language that isn't for simulation.
 

TrickyDicky said:
Verilog is now a subset of system verilog as of sv2005.

Vhdl is getting another release this year. Look forward to support in 2025.
Click to expand...

2025. Don't be ridiculous it'll be at least 2050
 

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