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Hi! May I know if what are the verilog code that are not synthesizable. It can be converted into the generic lib but there are no equivalent cell in my target library. For example:
Making a new library adding new cells is not our designing task. Let confirm with your manager or related people who can design with/without asyn reset FF.Hi All!
Yes I am talking about mapping it into my technology file. I have already read the datasheet of my library, it contains no async reset FF. What do I need to do? is it to make a new standard cell library or to revise my RTL code?