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[SOLVED] Statement inside CASE in VHDL

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dzafar

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Hello there,

My question is are statements inside a 'when' (under case statement) concurrent? i.e. in the image below (shown in red) if I change the order as follows, will the functionality still be the same?

F <= '1';
​
current_state := state1;

Untitled.png

Thanks in advance :)
 

They are effectively concurrent, order does not matter. The two ways you suggest will provide exactly the same result.
 
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    dzafar

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As long as the reset value of the state register (which you effectively abstract when using the enumerated type) remains the same - the order doesn't matter.
 

shaiko said:
As long as the reset value of the state register (which you effectively abstract when using the enumerated type) remains the same - the order doesn't matter.
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Only In this case.

The problem here can be an question about the differences between signals and variables.
If everything was a signal, then the order of the assignments is unlikely to make any differences.
But with variables, because they are assigned immediately, changing the code order can significantly affect behaviour.

To the OP: I suggest you stick ONLY with signals for now - variables can cause issues due to code order dependencies.
 
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    dzafar

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I suggest only using variables when they do not infer registers.

VHDL often lacks features that would be useful for design, like locally scoped signals.
 

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