Maximum/ typical current rating for each FPGA bank

Dear all,

I would like to know How I can calculate the maximum current rating for each FPGA bank. I am using spartan 6(lx45) FPGA.

Any help is going to be appreciated.

Regards,
Viya

Number of I/Os multiplied by the consumed current.
Just make sure that you don't exceed the current rating of each I/O, that you have proper noise decoupling and sufficient heat transfer...

Hi Shaiko,
Thank you for your reply. I have one more doubt. How can I calculate the current rating for the following voltage rail;
1. FPGA auxiliary voltage( 3.3V)
2. FPGA core voltage(1.2V)
3. FPGA PLL voltage(1.2V)

Regards,
Viya

As far as I remember, the vendor has power estimation tools that can help you with that.
Assuming proper data input to the these tools - the estimation accuracy can be quite decent (~25% is what I got) for design purposes.

Another (more accurate and hands on) alternative, will be to acquire an evaluation board with the FPGA you intend to use, connect an A meter in series to the nets in question and take measurements with a functioning design. I had to do it once for a project with very stiff constraints on FPGA current consumption (below 50uA). Didn't trust the estimation tool for such low values...

First comment, "current rating" is not the usual term to specify device current consumption in different operation conditions and might cause misunderstanding of your questions. "Current rating" is typically used to specify the permissible maximum and nominal operation current of various devices.

Particularly core and IO current consumption will strongly depend on operation conditions, external load, toggling frequency, number of utilized logic cells. That's the reason why they can't be specified with a single data sheet number. Using vendors power estimation tools is probably the best approach.

shaiko said:

As far as I remember, the vendor has power estimation tools that can help you with that.
Assuming proper data input to the these tools - the estimation accuracy can be quite decent (~25% is what I got) for design purposes.

Another (more accurate and hands on) alternative, will be to acquire an evaluation board with the FPGA you intend to use, connect an A meter in series to the nets in question and take measurements with a functioning design. I had to do it once for a project with very stiff constraints on FPGA current consumption (below 50uA). Didn't trust the estimation tool for such low values...

Click to expand...

Actually with a good set of test vectors (VCD) file (preferably with timing) from real world representative operation you can see results that are within a small <10% difference between the estimated and the board power consumption. I know this because we had a design that had a hard limit on the power we could draw. So the FPGA being the worst culprit for current draw was of course the one part that needed it's power numbers pinned down accurately. The typical values for current consumption were mostly within a few percent of the actual values measured on the board.

The original estimated values based on just the number of FFs, RAMs and the estimated toggle rate was closer to 40% accurate (spent a lot of time breaking down the toggle rates for the various blocks and the RAMs. There was only about 25% of the design that wasn't from actual design files, but put into the spreadsheet by hand. This was probably why the accuracy was so high at that point as opposed to the 25% you saw.

viyaaloth,

Everything written here is good and helpful - but I hope you understand that proper (quality oriented) design takes into consideration substantial de-rating values. With +30% being not uncommon for fields such as Aerospace/Defence/Medical.