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XilinxISE: Multiple designs in one project?

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Delsian

Delsian

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How I can describe different designs in Xilinx ISE project where all modules the same but one module is different? Is there any way to use "#define" and "#ifdef" in VHDL project?
 

Delsian said:
How I can describe different designs in Xilinx ISE project where all modules the same but one module is different? Is there any way to use "#define" and "#ifdef" in VHDL project?
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Depending on what you want to do, there is two ways to do it.

1. Use different model and use a configuration line. Currently ISE 6.3i
does not support different models within the same project. I mean if
you have two instantiation of the same entity. They have to be the same
model. But you can use different models for all of them. So if you want
, said instantiation 1 use model A and instantiation 2 use model B, you
are out of luck.

2. Use generic, for example

M_GEN: if <generic> = true generate

end generate M_GEN;

N_GEN: if <generic> = false generate

end generate N_GEN;

I use both methods depending on my needs. I like to use configuration
method but ISE has its limitations.

Hope this help.

Gunship
 

    Delsian

    Delsian

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