shanmei
Advanced Member level 1
As shown in the bellowing figure, I plot the intrinsic gain of three nmos transistor with 180nm process.
The Vds of the three transistors are set to 0.75V, and then I sweep the Vgs voltage of all of them from 0 to 1.5V. (The Y-aix is the intrinsic gain, and the X-aix is the Vgs.) Their size are 5/0.5, 5/0.5, and 50/10, with the um unit.
From the figure, it seems that the intrinsic gains are almost the same for the nmos transistors which are biased at the same Vgs and Vds, regardless of their size.
Anyone can explain that why the gain is independent of the size? Thanks.
The Vds of the three transistors are set to 0.75V, and then I sweep the Vgs voltage of all of them from 0 to 1.5V. (The Y-aix is the intrinsic gain, and the X-aix is the Vgs.) Their size are 5/0.5, 5/0.5, and 50/10, with the um unit.
From the figure, it seems that the intrinsic gains are almost the same for the nmos transistors which are biased at the same Vgs and Vds, regardless of their size.
Anyone can explain that why the gain is independent of the size? Thanks.