[SOLVED] floating point representation in FPGA

I'm developing a low cost ultrasonic anemometer using FPGA. The calculations include division and square root of fractional numbers which has to be coded using verilog. Can u suggest whether fixed or floating point representation will be convenient if low cost and accuracy are my primary concerns?

it is entirely based on your inputs.
What is the range of input numbers you want to divide and or find square root.?

based on that only , fixed or floating is selected.

In most cases (i.e. ignoring special values in the IEEE floating point standard such as infinity and NaN), the only difference between a fixed and floating point implementation is that with floating point you will add a little extra stage which locates the most significant set bit (i.e. the most significant '1', assuming unsigned numbers). The location of that bit then tells you the exponent of the floating point number. Then you retain as many mantissa bits (from the MSB down), which completes your floating point number.

This floating point representation basically gives you more dynamic range (i.e. you can handle a wider range of input and output values for a fixed number of mantissa bits used in your computation), but the two implementations could be virtually the same. If you need the extra dynamic range, then the conversion to floating point is worthwhile. If you don't, then it would be a waste of resources.

A more important consideration might be whether you can combine your division and your square root (depending on how they need to be applied in your application). It is often possible to combine these sorts of operations in a way that saves a significant amount of resource.