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Design verificattion in FPGA

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DeepikaA

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Hi all,


I am woking on FPGA and I am verifying my designs using chipscope. In this case I will set the input test patterns and I will verify the corresponding output. But the problem with this approach is that, it is time consuming.

So, I am searching for techniques to automate the design verification in FPGA. Can you please tell me the options available to automate the verification process and their pros and cons.

Thanks
 

So, I am searching for techniques to automate the design verification in FPGA.
Click to expand...

You can use self-checking test-benches. In such a TB the DUT o/p is compared with a pre-defined set of values through a compare logic and a single PASS/FAIL message is generated.
If you want to go further, you can write a Python script that initializes your test environment, runs the simulation for a desired interval, filters data from the simulation log files and writes out your custom log file.
Just run the .py script and go for a coffee break and when you come back just check the summary log file after the test is completed.
 
Chipscope is a debugging tool, not a verification tool. Using it for verification would be very time consuming.

You need to looking into writing self checking test benches as dpaul mantions above. If you verify the design as much as possible in simulation where you have full visability on all of the design, you can save time debugging on hardware.
 
DeepikaA said:
Hi all,

I am woking on FPGA and I am verifying my designs using chipscope.

Can you please tell me the options available to automate the verification process and their pros and cons.

Thanks
Click to expand...

First you need to prove your model using behavioral simulation. In case if you prefer DFT style testing, then Xilinx VIO is your only go. It has options to directly interact with your code in real time. The GUI allows you to read/write data to your logic where you prefer to attach a probe. Chipscope ILA probes are more of reading the values to check if it meets your expected behavior model in simulation. So, a behavioral simulation is must to cross verify with Chipscope.

Hope this helps.
 
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