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Clock input capacitance - discrepancy

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reddvoid

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Hi,
I have a post layout extracted netlist in which if I measure the input capacitance on the clock pin by simulation I am getting 1.58fF
and when I measure on schematic by simulation, I am getting 0.6fF and the parasitic cap. on the clock pin I am able to extract from .spf file which is 0.4fF

but 0.4fF + 0.6fF =1fF
and I am not able to trace from where the extra 0.58fF is coming from in the post layout extracted netlist.

so the schematic cap + Parasitic cap. should add up to post layout cap right ?
I am not able to trace where the remaining 0.58fF coming from in post layout cap.
 

Hi,

Can you show more detail about your design?
- may be digital design?
- I measure the input capacitance on the clock pin by simulation I am getting 1.58fF ==> by which tool?
- 0.6fF and 0.4fF ==> which tool?

If this is the digital design, you can use PrimeTime tool to get the net that connected to the clock pin by command "set net [get_nets -of_object [get_pins */CK]]".
Then, report the net by command "report_net $net -connection -verbose".
This report will show you the pin capacitance and parasitic capacitance on this net.

Regards
 

Hi,

I´m really not experienced in this field. My Idea: Is it possible that the miller effect introduces some additional capacitance?

Klaus
 

KlausST said:
Hi,

I´m really not experienced in this field. My Idea: Is it possible that the miller effect introduces some additional capacitance?

Klaus
Click to expand...

Hi, Yes, Miller cap capacitance has been taken care of.
 

The .spf file will contain only the parasitic's for metal/poly. That is the static capacitance associated with the pin. when you running the simulation, the Cgs,Cgd are all voltage dependent values. So you have to run the simulation by integrating the current that is going into the pin for PWL waveform going into the pin and then dividing it by voltage. This will also depend on the slew rate of the PWL which you are using. if you are using STA tool to do the capacitance measurement, then the .libs have input_rcvr_caps (C1, C2) which is voltage variable capacitance, so that will be the worst case pin cap in the tool analysis.

if you are 16nm or lower technology the differences will be more prominent.
 
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