Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to fix hold and setup at gated andnon gated clock

Status
Not open for further replies.
B

bhaskarg

Newbie level 4
Newbie level 4
Joined
Aug 22, 2016
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
31
dear all,

if i have 2 flip-flops ,
ff1 clock pin is connected to clk
ff2 clock pin is connected to gated clock.....

my doubt...
if i found either hold r setup violation on this path with repsect to +ve edge.. then how i can fix the violation

can any one guide me


thanks in advance
bhaskarg
 

A circuit an timing diagram would be needed to understand your problem. If setup and hold time violation can not be avoided(asychronous incoming signals) a synchronization with two flipflops in series could be used. The second flipflop uses a delayed clock, so that metastable states of the first flipflop a over.

Enjoy your design work!
 
thanks HTA....


one more doubt

what is the use of amobea view in the ENCOUNTER cadence

thanks in advance
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top