layout circuit principle effects (speed, power, noise & area)

can anyone pls explain some of the circuit principles affected by layout such as speed, power, noise & area??? Thank you!!!

Your question is general and it is not easy to answer it shortly. I assume that you mean the diffeerences between schematic and post-layout simulations.
Schematic only simulations takes into account only devices that are presented in schematic. But real (fabricated) device will have not only such elements,
but also so called parasitic ones. E.g. metal line has some resistance, this line creates capacitors with other metal lines or substrate/well (they are separated using di-electric).
Draine/source areas also create diodes with their substrates. Thus, paracitic capacitors consumes dynamic energy (power) connected with voltage change; they also decrease speed of the device. Reverse-biased diodes has leakage current, which also increase power consumption. Proper floor-planning of layout can minimize the area of the circuit.
It ia just very short and very general answer. The more detailed informartion can be found in books devoted to layout and circuit design.

thank you for the reply serfacy!!! I asked it in the sense like as you mentioned floor planning deals with area. I read if metal density is not met properly, dishing can occur sweeping away required metals and this increases the resistance through that metal and this affects/deals with power. Same way so could you give me a general basic list that affects
area
power
speed
noise

Like metal density for power, floor planning for area and so on...Becoz other than metal density der must be more layout factors that affect the power. What are some of those like that. Pardon me for not being clear in initial post. Thanks again!!!

If you make layout as small as possible (of course meeting DRC rules) the connection lines are shorter. So it seems that paracitic capacitors are decreased. But at the other hand the separatrion between metal paths is also smaller so the parasitic capacitance can even increase. So, one should decrease metal lines length and keep separation in reasonable value. Than the parasitic capacitance can be reduced. And because of that the speed increases and power decreases.
The smallest layout results that the power is dissipated in the smaller area, so the self-heating effect can increase tmeperature, so, the power losses will also increase.
I think that noise is mainly caused by trasistors ans theirs parasitics. For example, when you use multi-finger transistors, the drain/sources areas are shared. As the result the drain/sources area is smaller with comparison to transistors made separately. As the results noise is also reduced.