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[SOLVED] What is the shortest way to assigned unconstrained array to constrained array in VHDL

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matrixofdynamism

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In a function the parameter is unconstrained std_logic_vector called slv

Within the function I must assign the slv to a another std_logic_vector variable of length 4. Lets call this slv_temp: std_logic_vector(3 downto 0)

Now I want to make sure that slv is no more than 4 bits. I use assert statement:

assert slv'length <= 4 report "function parameter cannot be more than 4 bit long" severity error;

Later I do this:

if slv'length < 4 then

else

end if;
 

for this case:
Code: 
function example(x : std_logic_vector) return std_logic_vector is
  variable x_nml(x'length-1 downto 0) := x; -- I think this works.  if not it becomes the first line in the function.
  variable result(3 downto 0) := (others => '0'); -- assuming default '0'
begin
  assert x'length <=4 report "this is bad" severity error; -- or failure.
  result(x_nml'range) := x_nml;  -- assuming msb's are not modified.
  -- any logic done, otherwise this is just zero-extending.
  return result;
end function;

I always suggest normalizing any unconstrained input to N-1 downto 0, with the exception of sfixed/ufixed where the indicies are important.
 
matrixofdynamism said:
In a function the parameter is unconstrained std_logic_vector called slv
Within the function I must assign the slv to a another std_logic_vector variable of length 4. Lets call this slv_temp: std_logic_vector(3 downto 0)
Now I want to make sure that slv is no more than 4 bits. I use assert statement:
assert slv'length <= 4 report "function parameter cannot be more than 4 bit long" severity error;
Click to expand...
This suggests that slv is not defined correctly. It should be defined as a four bit vector in the interface rather than as an unconstrained vector.

Kevin Jennings
 

Basically I am writing a function that shall take a std_logic_vector of any length and return a string representing its hexadecimal equivalent. Therefore, I have created a hierarchy of functions where one calls the other to achieve this task. The idea is to divide the task into smaller tasks and these functions representing the smaller tasks can be used on their own as well. It has provided me with a way to practice certain aspects of my VHDL skills.

Now the specific function that this question is related to, takes a std_logic_vector upto 4 bits long and returns the single character hexadecimal translation of it. I want this function to be able to take 1 to 4 bit std_logic_vectors. However, if a longer std_logic_vector is passed to it, it must generate an error message which is why I have this assert statement.

The main function get_hex_string_from_slv, calls get_hex_char_from_slv being discussed here multiple times and fills in a string variable which is then returned at the end.
 

matrixofdynamism said:
Basically I am writing a function that shall take a std_logic_vector of any length and return a string representing its hexadecimal equivalent. Therefore, I have created a hierarchy of functions where one calls the other to achieve this task. The idea is to divide the task into smaller tasks and these functions representing the smaller tasks can be used on their own as well. It has provided me with a way to practice certain aspects of my VHDL skills.

Now the specific function that this question is related to, takes a std_logic_vector upto 4 bits long and returns the single character hexadecimal translation of it. I want this function to be able to take 1 to 4 bit std_logic_vectors. However, if a longer std_logic_vector is passed to it, it must generate an error message which is why I have this assert statement.

The main function get_hex_string_from_slv, calls get_hex_char_from_slv being discussed here multiple times and fills in a string variable which is then returned at the end.
Click to expand...

These functions already exist.
For VHDL 2002 and similar:

You can use the std_logic_textio library (non standard, but useful) and use the write, hwrite and owrite procedures to write a std_logic_vector to a line (with equivolent read, oread and hread functions)

In 2008:
The functions above are included as standard in the std_logic_1164 package, along with functions to_string, to_hstring and to_ostring.
These functions also exist for unsigned, signed, ufixed and sfixed and bit_vector.
 

I needed conversion to string for the report commands to write to transcript
 

matrixofdynamism said:
I needed conversion to string for the report commands to write to transcript
Click to expand...

As I already stated, the to_string/to_hstring/to_ostring do this for you:

Code: 
report "There was an error : " & to_hstring(my_slv);
 

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matrixofdynamism said:
Basically I am writing a function that shall take a std_logic_vector of any length and return a string representing its hexadecimal equivalent. Therefore, I have created a hierarchy of functions where one calls the other to achieve this task. The idea is to divide the task into smaller tasks and these functions representing the smaller tasks can be used on their own as well. It has provided me with a way to practice certain aspects of my VHDL skills.

Now the specific function that this question is related to, takes a std_logic_vector upto 4 bits long and returns the single character hexadecimal translation of it. I want this function to be able to take 1 to 4 bit std_logic_vectors. However, if a longer std_logic_vector is passed to it, it must generate an error message which is why I have this assert statement.
Click to expand...
To simply accomplish the function, then the VHDL-2008 functions are the way to go as TrickyDicky posted. From the 'provided me with a way to practice certain aspects of my VHDL skills' perspective, I would make the following suggestion:

- Make your functions work with any size vector. That was what was implied when you made slv an unconstrained vector as well as what you just stated. An assertion based on the input vector size should not be part of that function since, by erroring out, it means that your function does not work with any size vector. If you're given a vector longer than four bits, then you can use recursive calls to your function (others prefer loops) until the vector is four bits or less.

Kevin Jennings
 
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