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Why verilog is known as RTL language?

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akrlot

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verilog hdl

hi;
why verilog is called as RTL langage?
could you give links/ebooks about verilog.Thx
 

verilog hdl

When Verilog is used in RTL level then flip-flops (registers) are used. For this reason is called Register Transfer Level.
For ebooks have a look at the forum for Ebooks Upload/Download.
 

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    akrlot

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Re: verilog hdl

Not only verilog but also VHDL, if the code you write is based on Register Transfer Level, it is called RTL.
 

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    akrlot

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Re: verilog hdl

there are some books on verilog in the forum,u could search
 

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    akrlot

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Re: verilog hdl

adap said:
When Verilog is used in RTL level then flip-flops (registers) are used. For this reason is called Register Transfer Level.
For ebooks have a look at the forum for Ebooks Upload/Download.
Click to expand...


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yes, what adap mentioned is what we also called "synthesizable verilog code". at RTL level, logic change depends on the clock for synchronize design. there is another level called behavirol level, in this level you just describe how ur design may function, it doesn't have to be in logic and register level, hence it's not synthesizable code.



hope i help u.

regards,
smart
 

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    akrlot

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Re: verilog hdl

h**p://www.dientuftp.com/down/verilog
 

verilog hdl

verilog can be used for RTL description in front end design, besides, verilog can be for behavial description, extent to a good verifacation language via PLI, and many netlist can be in a verilog format.
 

Re: verilog hdl

Any code that is synthesizable is called RTL. means register transfer where the created code synthesize to registers and the flow of data through that registers
 

Re: verilog hdl

Check out verilog by samir palnitkar....i think ur doubts wil be cleared...u could search for it in this forum
 

Re: verilog hdl

all synthesizable HDL are called RTL . BOOKs u can search from forum ,net......
 

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