Methods of opening a file in VHDL

shaiko · Jul 18, 2016

Hello,

In pages 9 and 10 of this post:
**broken link removed**

The author mentions 2 methods of opening a file:
1. Using the "file_open" function (page 9).
2. Implicitly in the declaration section (page 10).

When would you choose one method over the other?

TrickyDicky · Jul 19, 2016

Use 1 when you want to open a file at a given point in simulation time (its a procedure, not a function)
Use 2 when you want a file open from the start of simulation.

shaiko · Jul 19, 2016

Thanks.
Is there any reason why I shouldn't always use the second method (open the file at start, close it in the end)?

TrickyDicky · Jul 19, 2016

No, unless you need some runtime information for the file name.
Its a bit of an odd question, because it really depends on what you're doing.

Most people just use the 2nd method.

shaiko · Jul 19, 2016

I have a text file of signed integers that looks like this:

Code:

-100 5 500
-27 44 -99
100 200 -300

Using VHDL 2008 - I want to read the numbers into my testbench.
This is what I wrote:

Code:

reading_from_file : process (clk) is
file my_file : integer open read_mode is "C:\some_location\some_file" ; 
...

This is the Modelsim message I get:

FILE declaration must have a subtype indication that is a file type.

What type files are possible?

TrickyDicky · Jul 19, 2016

You can declare any file you want, but it must be a file type:
type int_file_t is file of integer;

then :

file my_file : int_file type open read_mode is "some_file";

but what you have is likely a text file, so you need:

file my_file : text open read_mode is "some_file";

its much easier to read text files as there are procedures already declared for reading all of the standard types (integer, bit, std_logic(_vector), signed/unsigned) from text files.

- - - Updated - - -

If you dont use text, VHDL does not define how the output/input files will be formatted, thats down to the simulator, so reading/writing binary from one simulator can produce different files from another simulator, causing incompatabilities.

shaiko · Jul 19, 2016

Thanks.
This is what I wrote:

Code:

signal incoming_pixel : integer ;		
signal pixel_out :	integer ;		
		
reading_from_file : process ( clock ) is
file text_file : text open read_mode is "C:\location\some_text_file.txt" ; 
variable current_line : line ;
variable incoming_pixel : integer ;
begin
   if ( not endfile ( my_file ) ) then
      if rising_edge ( stimulus_in_clock ) then
         readline ( my_file , current_line ) ;
	 read ( current_line , incoming_pixel ) ;	
      end if ;
   end if ;	
   pixel_out <= incoming_pixel ;
end process reading_from_file ;

pixel_out strobes:
100 -27 100
Only the leftmost column.

What did I do wrong?

TrickyDicky · Jul 19, 2016

you only do 1 read per line, hence you only read the left most value.
You will need to either do multiple reads per line, or make your file 1 value per line.

shaiko · Jul 19, 2016

You will need to either do multiple reads per line

This is what I'd like to do.
Can you please post an example of my code - modified to do that?

FvM · Jul 19, 2016

As said, do multiple reads per line.

Code:

readline ( my_file , current_line ) ;
read ( current_line , incoming_pixel1 ) ;
read ( current_line , incoming_pixel2 ) ;
read ( current_line , incoming_pixel3 ) ;

You won't need to ask if you reviewed the description of textio package in VHDL LRM.

TrickyDicky · Jul 19, 2016

Code VHDL - [expand]
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reading_from_file : process ( clock ) is
file text_file : text open read_mode is "C:\location\some_text_file.txt" ; 
variable current_line : line ;
variable incoming_pixel : integer ;
 
variable pel_cnt : integer := 0;
begin
    if rising_edge ( stimulus_in_clock ) then
         
      if ( not endfile ( my_file ) ) then
         if pel_cnt = 0 then
            readline ( my_file , current_line ) ;
         end if;
         
         read ( current_line , incoming_pixel ) ;   
         
         pel_cnt := (pel_cnt + 1) rem 3;
         pixel_out <= incoming_pixel ;
      end if ;
   end if ; 
   
end process reading_from_file ;

- - - Updated - - -

FvM said:
As said, do multiple reads per line.

Code:

readline ( my_file , current_line ) ; read ( current_line , incoming_pixel1 ) ; read ( current_line , incoming_pixel2 ) ; read ( current_line , incoming_pixel3 ) ;

You won't need to ask if you reviewed the description of textio package in VHDL LRM.

Or just any VHDL Textio tutorial on the internet - plenty of code examples....

shaiko · Jul 19, 2016

Thanks TrickyDicky.

I tried the code and it works.
I wanted to add a control signal to this process that asserts when pixel_out is valid and de-asserts after the last number from the file has been read out.
This is what I wrote:

Code:

reading_from_file : process ( reset , clock ) is
file text_file : text open read_mode is "C:\some_location\some_file.txt" ;
variable current_line : line ;
variable pixel : integer ;
variable pixel_counter : integer := 0 ;
variable valid_data : std_logic := '0' ;
begin
   if reset = '1' then
      valid_data := '0' ;
      valid_data_out <= valid_data ;
   elsif rising_edge ( clock ) then
      if ( not endfile ( text_file ) ) then
         valid_data := '1' ;
	 valid_data_out <= valid_data ;
	 if pixel_counter = 0 then
	    readline ( text_file , current_line ) ;
	 end if;
         read ( current_line , pixel ) ;   
	 pixel_counter := ( pixel_counter + 1 ) rem 3 ;
	 pixel_out <= std_logic_vector ( to_signed ( pixel , pixel ' length ) ) ;
      else
         valid_data := '0' ;
	 valid_data_out <= valid_data ;
      end if ;	
   end if ; 
end process reading_from_file ;

The result I got was almost to my satisfaction - but not quite...
Because of the sensitivity list, the signal is updated one clock after the last number in the file.
I think I can get around this with adding a row counter (this way I'll know when the file is going to end). But is there another way?
The edge where I want to de-assert the valid signal is marked in red.

- - - Updated - - -

Update:

I changed my code by moving up "( not endfile ( text_file ) )" for it to have precedence over "rising_edge ( clock )":

Code:

reading_from_file : process ( reset , clock ) is
file text_file : text open read_mode is "C:\some_location\some_file.txt" ;
variable current_line : line ;
variable pixel : integer ;
variable pixel_counter : integer := 0 ;
variable valid_data : std_logic := '0' ;
begin
   if reset = '1' then
      valid_data := '0' ;
      valid_data_out <= valid_data ;
   elsif ( not endfile ( text_file ) ) then
      if rising_edge ( clock ) then
        valid_data := '1' ;
	    valid_data_out <= valid_data ;		  
	    if pixel_counter = 0 then
	       readline ( text_file , current_line ) ;
	    end if;
            read ( current_line , pixel ) ;   
	    pixel_counter := ( pixel_counter + 1 ) rem 3 ;
	    pixel_out <= pixel ;
      end if ;
   else
      valid_data := '0' ;
      valid_data_out <= valid_data ;
   end if ;	
end process reading_from_file ;

Now I see something really strange.
valid_data_out drops on the falling edge.
What's the reason for such behavior??

TrickyDicky · Jul 19, 2016

Becase you have clock in the sensitity list, any 'event on the clock is going to cause the process to be evaluated. Hence why you get falling edge behaviour.

Tetik · Jul 19, 2016

Why not in your else statement you don't assign valid_data_out to '0' instead of valid_data.

valid_data_out <= '0'; -- valid_data;

shaiko · Jul 21, 2016

1. Do I need to close the file after I'm done using it? If so, what's the syntax?
2. the function "endfile" is very usefull. Is there a similar function to know that a line has ended ?

TrickyDicky · Jul 21, 2016

1. It depends. If you want to start from the beginning of the file again, then yes. But all files will be closed automatically at the end of simulation. To close a file:
FILE_CLOSE(my_file);

2. No, but you can check if a read from a line was good or bad (ie. what you tried to read doesnt exist on the line)

Code VHDL - [expand]
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variable good : boolean;
variable l : line;
 
.......
 
 
read(l, ip, good);
 
if not good then
  -- do something because the line ended
end if;

I highly suggest you get some form of reference guide, as your questions are answered in many many examples and references on the web - it wouldnt hurt you to use google (or a reference guide) more often before coming straight to the forums.

I recommend the Doulos Ones (every entry contains a code example):
**broken link removed**

shaiko · Jul 21, 2016

I've read a lot of material on the subject as well as other edaboard / stackoverflow posts before posting.
The thing is - there's too much information. some of it is "half good". A lot of old posts are based on VHDL 87 or 93 with methods that maybe obsolete if you're dealing with VHDL 2008 (as it can be done much simpler).

Also, much of what I've seen online leaves room for ambiguous interpretation. Therefore for me, when it comes to learning new things and finding answers to specific questions - there's nothing like interacting with a real person who's an expert in the field.
Thanks again for your kind help.

TrickyDicky · Jul 21, 2016

I highly recommend the doulos golden reference guide...

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