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[SOLVED] EMC friendly layout and split planes?

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I understand that it’s bad practice to run a high speed signal over a plane that is interrupted.
Assume we have a multi-layer board and the ground plane is solid (covers the entire board with no interruptions. This is a common ground for both digital and analog.

Now let’s say half the board is powered from 3.3V (digital), and the other half 5V (analog), so I use one split plane that is half 3.3V and the other half 5V.
So if I now have high speed lines let’s say 10MHz SPI signals passing over the 3.3V/5V split plane is this a problem or does the uninterrupted ground plane make the split power plane a non-issue?
 

It is certainly a potential problem, which can be minimised by placing small caps between the two power planes right next to the trace in question (You should also probably do this when transitioning between using the power plane as a reference and using the ground plane (And it does not hurt your decoupling any in this case).

Now the other (and far more important) question is not how fast the clock is, but how fast the edges are?
10MHz, with source termination or a slow IO driver you may get away with, 10MHz with a stiff fpga IO block driving the line directly with a 0.5ns rise time would be a very different thing.
 
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Dan Mills said:
It is certainly a potential problem, which can be minimised by placing small caps between the two power planes right next to the trace in question (You should also probably do this when transitioning between using the power plane as a reference and using the ground plane (And it does not hurt your decoupling any in this case).

Now the other (and far more important) question is not how fast the clock is, but how fast the edges are?
10MHz, with source termination or a slow IO driver you may get away with, 10MHz with a stiff fpga IO block driving the line directly with a 0.5ns rise time would be a very different thing.
Click to expand...

What value capacitor is appropriate?
 

You didn't mention a PCB stack-up.

If you have a continuous ground plane, I would expect that the power planes are bypassed to it by various distributed capacitors, located e.g. at every IC power pin. In this case, the power planes acts mostly like a ground plane without additional capacitors.
 
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