how to control xilinx axi4lite fifo?

Hi.

I'm looking for some tutorial or example to control AXI4LITE FIFO.
I'm familliar with native fifo but AXI4 does not.
So I'm looking for some example about how to control AXI4LITE FIFO of the xilinx.

Can you help me please?

I just make one fifo then there is S_AXI and M_AXI port.
I don't know how to read and write data from fifo.
Does anyone please help me?

Just checked and the FIFO Generator wizard produces a simulation testbench fifo_generator_vlog_beh.v (I have my IP generated in Verilog). So why do you need a example if there's one already produced by the tools?

Did you ever look in the subdirectories of the produced core before posting on edaboard?

ads-ee said:

Just checked and the FIFO Generator wizard produces a simulation testbench fifo_generator_vlog_beh.v (I have my IP generated in Verilog). So why do you need a example if there's one already produced by the tools?

Did you ever look in the subdirectories of the produced core before posting on edaboard?

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Thanks ads-ee, yes I knew that, but My fifo generator testbench has only vhdl version. Also the problem is that I'd like to control in the bus vivado bus architecture. So I need to know how to control that IP on the zynq vivado system.
Firstly I'll check how to get verilog version. My coregen is at the ISE 14.7and 9.3version. As I know, I can have an option about verilog and vhdl in the Project->project option-> generation ( verilog). I did. But the outs are all of vhdl files.

Can you let me know what you have a tool version?

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How can you get as verolog? As I know Xilinx LogiCOREIP FIFO Generator is support vhdl not verilog.

u24c02 said:

So I need to know how to control that IP on the zynq vivado system.
Firstly I'll check how to get verilog version. My coregen is at the ISE 14.7and 9.3version.

Click to expand...

ISE and Vivado are two completely different tool suites and the IP is not supposed to be swapped between tools.

At the absolute minimum did you already read the AXI spec from Xilinx? If not read at least that. If you want to learn how to use AXI get the AXI spec from ARM.

ads-ee said:

ISE and Vivado are two completely different tool suites and the IP is not supposed to be swapped between tools.

At the absolute minimum did you already read the AXI spec from Xilinx? If not read at least that. If you want to learn how to use AXI get the AXI spec from ARM.

Click to expand...

First of all, I want to get your" fifo_generator_vlog_beh.v" files. It seems that you get some verilog files from coregen.
So Would you let me know what kind of tool and version you used to get that verilog files? Is this a fifo right? And AXI4 interface type?

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Thanks my problem is that the fifo have 2 axi port, one is s_axi_xxx and the other is m_axi_xxx in the one. I know AXI specipication but as you can see the fifo generator ip symbol then it's hard to understand how the signals are transactioning to read and write. Can you give me any hint to undeerstand how to handle that signals to read and write? Timing diagram is also good.