mohsen68sh
Junior Member level 1
Hello all,
i am trying to use a FIR IP core 5 in spartan3.
i designed and quantized filter in matlab and used core generator to create it.
i want my system to work in 40MHz clock frequency and 10 MHz input sampling frequency. input and output should be 12 bit.
i changed all the parameters but the output of simulation always look weird!!
when i look at the output, i think that it looks like the input but FIR filter cuts down both sides of input.
any help is appreciated.
my test bench is here (i know its unprofessional)
i am trying to use a FIR IP core 5 in spartan3.
i designed and quantized filter in matlab and used core generator to create it.
i want my system to work in 40MHz clock frequency and 10 MHz input sampling frequency. input and output should be 12 bit.
i changed all the parameters but the output of simulation always look weird!!
when i look at the output, i think that it looks like the input but FIR filter cuts down both sides of input.
any help is appreciated.
my test bench is here (i know its unprofessional)
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 module FIR_tb; // Inputs reg clk; reg [11:0] data_in; reg [11:0] d_in [0:198]; integer index; integer f; // Outputs wire [11:0] data_out; // Instantiate the Unit Under Test (UUT) main_FIR uut ( .clk(clk), .data_in(data_in), .data_out(data_out), .rfd(rfd), .rdy(rdy) ); initial begin // Initialize Inputs #100; clk = 0; data_in = 0; f=$fopen("D:\output.txt"); $readmemh("C:\detout_hex.txt",d_in); index = 0; end always @(clk) begin clk <= #12.5 ~clk; end always @(posedge rfd) begin data_in = d_in[index]; index=index+1; $fmonitor(f,"%d",data_out); end endmodule
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