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what is the wrong in this code

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Serwan Bamerni

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hello everyone

I wrote the following code but I get a wrong output and a huge warnings

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;



entity memory_controller is
    Port ( data_in 	: 			in  	STD_LOGIC_VECTOR (7 downto 0);
           read_add 	: 			out  	STD_LOGIC_VECTOR (7 downto 0);
           write_add_a_ind : 	out  	STD_LOGIC_VECTOR (7 downto 0);
           write_add_b_ind : 	out  	STD_LOGIC_VECTOR (7 downto 0);
           write_add_c_ind : 	out  	STD_LOGIC_VECTOR (7 downto 0);
           write_add_d_ind : 	out  	STD_LOGIC_VECTOR (7 downto 0);
           data_out : 			out  	STD_LOGIC_VECTOR (7 downto 0);
           wmae : out  STD_LOGIC;
           wmbe : out  STD_LOGIC;
           wmce : out  STD_LOGIC;
           wmde : out  STD_LOGIC);
end memory_controller;

architecture Behavioral of memory_controller is

	SIGNAL mem_sel: 	STD_LOGIC	:= '0';
	SIGNAL gro_sel: 	STD_LOGIC	:= '0';
	SIGNAL write_mem_a_count: 	STD_LOGIC_VECTOR (7 downto 0):= (others => '0');
	SIGNAL write_mem_b_count: 	STD_LOGIC_VECTOR (7 downto 0):= (others => '0');
	SIGNAL write_mem_c_count: 	STD_LOGIC_VECTOR (7 downto 0):= (others => '0');
	SIGNAL write_mem_d_count: 	STD_LOGIC_VECTOR (7 downto 0):= (others => '0');
	SIGNAL mem_group_count: 	STD_LOGIC_VECTOR (8 downto 0):= (others => '0');
	SIGNAL read_ind: 	STD_LOGIC_VECTOR (7 downto 0):= (others => '0');

begin

	data_out <= data_in;
	
	write_add_a_ind 	<= write_mem_a_count;
	write_add_b_ind 	<= write_mem_b_count;
	write_add_c_ind 	<= write_mem_c_count;
	write_add_d_ind 	<= write_mem_d_count;
	
mem_con: PROCESS (data_in)

	VARIABLE ci: 	STD_LOGIC_VECTOR (1 downto 0);

	begin

	ci := gro_sel & mem_sel;
	
	CASE ci IS
		
		WHEN "00" => 
			wmae <= '1';
			wmbe <= '0';
			wmce <= '0';
			wmde <= '0';
			write_mem_a_count <= std_logic_vector(unsigned(write_mem_a_count) + 1 );

		WHEN "01" => 
         wmae <= '0';
			wmbe <= '1';
			wmce <= '0';
			wmde <= '0';
			write_mem_b_count <= std_logic_vector(unsigned(write_mem_b_count) + 1 );
		
		WHEN "10" => 
   		wmae <= '0';
			wmbe <= '0';
			wmce <= '1';
			wmde <= '0';
			write_mem_c_count <= std_logic_vector(unsigned(write_mem_c_count) + 1 );
   
		WHEN OTHERS => 
			wmae <= '0';
			wmbe <= '0';
			wmce <= '0';
			wmde <= '1';
			write_mem_d_count <= std_logic_vector(unsigned(write_mem_d_count) + 1 );	
	 
	END CASE;
	
	mem_sel <= not(mem_sel);

	mem_group_count <= std_logic_vector(unsigned(mem_group_count) + 1 );	
	
	if (mem_group_count(8) = '0') then
	
	gro_sel <= '0';
	
	else 
	
	gro_sel <= '1';
	
	end if;
	
	if (mem_group_count(8) = '1') then
	
	read_add <= read_ind;
	
	read_ind <= std_logic_vector(unsigned(read_ind) + 1 );	

	else
	
	null;
	
	end if;
	
	end process mem_con;	
	
end Behavioral;

I suppose that the output should be at first data in
wmae = 1
and
wmbe = 0
but it was opposite

and
write_add_a_ind = 00000000
but it will be = 00000001

also
write_add_b_ind will be 00000001
while it should be not changed

please can any one help me with this errors
 

Serwan Bamerni said:
hello everyone

I wrote the following code but I get a wrong output and a huge warnings
<snip>
please can any one help me with this errors
Click to expand...
1. Write a testbench
2. Start up the simulator and put a breakpoint in at the first line of the process
3. Single step through the process to find out where the outputs are being assigned the values that you think are not correct.
4. Modify your source code to fix the errors you found in step #3.
5. Iterate on steps #2 thru 4 until all outputs are to your liking in step #3.
6. Done

Kevin Jennings
 
1.) missing inputs in sensitivity list. a testbench will be misleading.
2.) x= not x inside a non-clocked process.
3.) x = x+1 inside a non clocked process.
 
vGoodtimes said:
1.) missing inputs in sensitivity list. a testbench will be misleading.
2.) x= not x inside a non-clocked process.
3.) x = x+1 inside a non clocked process.
Click to expand...

that is mean, I should add a clock

thanks for your help
 

Serwan Bamerni said:
that is mean, I should add a clock

thanks for your help
Click to expand...
That is mean!? (this says you think vGoodtime was not being nice to you)

I think you meant to say "Does this mean, I should add a clock?" (note the ? punctuation for a question, instead of a statement)


VHDL == VHSIC Hardware Description Language.

Hardware counters are memories with logic that makes them count up in binary. The memory is either Flip-flops, RAM, or Latches (bad idea in FPGAs). Your implementation is attempting to make a latch based counter (very bad) that isn't even structured properly to make it a latch.

You should use a clock and flip-flops for the counter.
 

@Serwan:

VHDL/Verilog are both simulation-first languages that also allow you to describe hardware. The sensitivity list is used by simulation to determine when to run the code inside the process. This is an anti-feature that is slowly being removed by new features in Verilog-2001 and VHDL-2008. The synthesis tool ignores the sensitivity list as much as possible.

In this case, the logic seems to mostly work in simulation because the sensitivity list doesn't include all signals that have their values used in the process. Adding them in should result in the values changeing rapidly in the simulation, or the simulation detecting a combinatorial loop. I've never tried this, so I don't know the exact behavior. It should be clear that this won't in the simulation at that point.

You should add a clock, as you are trying to generate memory elements. The current design method is to use the rising edge of a clock, and to have most signals in the design change at the rising clock edges.
 

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