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Help: TCP/IP implementation for Stratix IV

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sharifa

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Hello,

I want to implement a TCP/IP for my FPGA board Stratix IV, I been following a tutorial in Altera "Using the NicheStack TCP/IP Stack - Nios II Edition". I want to start with something that is more understandable.

Please guide me on where to start to implement a TCP/IP for Stratix IV board.

Thanks in advance
 

shaiko said:
What speeds are you looking to achieve?
Click to expand...

sorry am quite new in this field am willing to implement a TCP/IP runs over 10/100/1000 Mbps Ethernet.

I was using Qsys and Nios 2 to explore how can I implement the TCP/IP stack on FPGA, as I understood that I have to implement the PHY layer probably ethernet using Verilog . Then embed a processor core like the Nios2 which will run the TCP/IP stack that I program using "standard" C.

am I correct in that ? if so, please guide on how to start or at least if there are tutorials to follow
 

shaiko said:
I strongly doubt that a Nios II will be enough to do TCP/IP at 1G or even at 100M.
You'll probably have to offload the protocol stack into hardware.

I've seen a 1G TCP offload engine implemented on a Stratix 4 - but it was all in hardware.
Read this:
https://www.nanogrids.org/jaidev/papers/ispass03.pdf
Click to expand...


I never used offload nor tried it before and have no idea how to do it or start with it so I worry that I wont be able to implement it before the deadline, is there any other possible way to implement a TCP/IP software stack in Stratix IV?!
 

With the absence of a hard core processor on board - a soft core (NIOS) + FPGA logic is probably the easiest way to go.
But again, the feasibility of the solution depends on the speeds you want to achieve.
You have to establish the project goals before you start R&Ding.
 
TCP/IP was originally designed for mostly CPU based designs. If you don't need performance, start there.

You can also use other protocols, like UDP, in many places.
 
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