Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Can metastability occur on a latch ?

Status
Not open for further replies.
There is no Metastability, but there is possibility of glitch at the latch output in case Enable and Data pins switching at the same time.
 

mr_vasanth said:
Even if the input changes close to the closing edge of the latch enable also metastability will not occur ?
Click to expand...

As I mentioned, if data and enable change together, or say very closed to each other, we only can see a glitch at the output.
There is no data lost of signal wrong level after that.
 

You can build a flip flop out of two latches with an inverter on one of the enables so yes a latch can go metastable. That happens inside the latches in a flip flop when the flop goes metastable.

Any time you try to change the state of a latch but remove the gate to soon then you run the risk that the latch will be in the process of switching and then not have enough input to guarantee to finish the transition. The feedback loop in the latch then forces to one state or the other but may take longer than expected to get there. That is metastability.

John Eaton
 
jt_eaton said:
You can build a flip flop out of two latches with an inverter on one of the enables so yes a latch can go metastable. That happens inside the latches in a flip flop when the flop goes metastable.

Any time you try to change the state of a latch but remove the gate to soon then you run the risk that the latch will be in the process of switching and then not have enough input to guarantee to finish the transition. The feedback loop in the latch then forces to one state or the other but may take longer than expected to get there. That is metastability.

John Eaton
Click to expand...

Hi John,

I completely agree with your response. But can a standalone latch in the design go metastable ? I am skeptical about that because a standalone latch also involves setup and hold check time.
 

But can a standalone latch in the design go metastable ?
Click to expand...
Yes, if the latch enable is deasserted near data edge and setup or hold time are violated.
 

FvM said:
Yes, if the latch enable is deasserted near data edge and setup or hold time are violated.
Click to expand...

Thanks FvM. I believe if data edge changes near latch enable assertion it will not go metastable as the latch can borrow time when it is open. Metastability is possible only during latch enable deassertion. Is my understanding correct?
 

Latch will go metastable at the closing edge, not the opening edge. It can borrow time only for the opening edge. When data toggles near the closing edge, it can go metastable.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top