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[SOLVED] 50ns, 7V spike on power-up of 3v3 supply

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I have a LMZ14201 buck converter circuit (3.3V dc output), the output is well behaved when running, it has a soft start feature and ramps up very nicely. However sometimes on power-up (perhaps 1 in 10), prior to the soft start circuit and exactly at the moment of energization there is a short spike, sometimes two of them that last about 50nS at the 3.3V output, the peak voltage is about 7V. This circuit powers various digital IC's and I want to make sure they don't get damaged from these 50ns spikes.

The energy would obviously be quite low because of the short duration, should I be concerned and add a TVS on the output, or are these spikes too short to be concerned about?

When the spikes occur they are approximately where the red bar is in the first image.
 

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Unknowns are your on / off power dwell times and the soft start initial temperature while the random effects may be clock phase on the switch... and your design details with various loads
 

Show us your schematic.
You might try adding a 0.1uF ceramic cap with short leads from output to ground, in parallel with the output capacitor.
 

what is Vin(ac). In bad case, u didn't given details on How Ven pin is driven? After enable crosses it's threshold 1.18V, If UVLO conditions met, SS circuit starts charging soft-start capacitor and voltage starts rising.
You got issue before EN is enabled or before?
 
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The schematic is more or less from the datasheet. C4 is ceramic.

- - - Updated - - -

malli_1729 said:
what is Vin(ac). In bad case, u didn't given details on How Ven pin is driven? After enable crosses it's threshold 1.18V, If UVLO conditions met, SS circuit starts charging soft-start capacitor and voltage starts rising.
You got issue before EN is enabled or before?
Click to expand...

The spike occurs before Vin reaches 1.18V

Vin can be anywhere from 20-28Vac
 

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With C4 being ceramic and a 50ns output pulse (20MHz) the 100uF will be no doubt inductive so you have no effective filtering.
It will depend on type but X5R and Y5 types reduce in SRF 1 decade for every 2 decades in C value rise.
Add a 0.1uF plastic in parallel. or similar.

There may be other reasons.
 
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Tony is correct, there may be other reasons.
The first suspect is the board layout...would you kindly show it, top and bottom layers? (or any internal layers for a multilayer board).

Please highlight the ground paths.

What I think could be happening, is that high current spikes could be coupling through the ground return paths.
 
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LAYOUT1.pngLayout below:

Orange is top
Light blue is midlayer for 3.3V output (solid plane)
Tan is ground plane, as is Bottom dark blue not shown that covers entire board.
 

not for inductance but the pads certainly aren't ideal for soldering without thermal isolated pads to a massive heatsink.

yes I suggested 0.1 plastic, they used 1uF. similar effect to lower Z(f) at >10MHz
 
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what is CDBHM2100 ? Is it Bridge rectifier?
Did you saw any sharp pulses on Vin of U4
 

The same parallel method of caps separated by decades in value is used on the input, to also reduce the bridge pulse current ripple from ESR*Iavg/%duty cycle which creates pulse voltages.
 

malli_1729 said:
what is CDBHM2100 ? Is it Bridge rectifier?
Did you saw any sharp pulses on Vin of U4
Click to expand...

Yes a bridge rectifier.
You can see the input waveform in the scope capture (original post)
 

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