Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Moved]: RC settling and the miller effect

Status
Not open for further replies.

diarmuid

Full Member level 2
Full Member level 2
Joined
Aug 4, 2011
Messages
143
Helped
10
Reputation
20
Reaction score
9
Trophy points
1,308
Location
Dublin, Ireland
Activity points
2,429
Here is a question which has been bothering me about caps:

1.) Charge stored on a cap is given by Q = C. V. Therefore if I double the voltage across a cap, I double
the amount of charge it can store hence doubling its effective capacitance. This is the idea behind the
Miller effect.

2.) The charging up of a series RC circuit is given by vo(t) = vi(t).[1-e^(-t/RC)] and from this we say
that the rise time of such a circuit is completely determined by its RC time constant.

My question then is:

If I am charging up a series RC circuit where C is connected between vout and ground, circuit charges in a certain time.
Say now C is connected between vout and a voltage > ground. By virtue of 1 above, would this not make C appear
smaller and hence reduce the rise time over the first case?

Likewise, if I connect C between vout and a voltage < grount. By virtue of 1 above, would this not make C appear
larger and hence increase the rise time over the first case?

In simulations I see identical rise times so I am missing something very basic here. Any ideas?

Thanks,

Diarmuid
 

Re: RC settling and the miller effect

"voltage < or > ground" can be a DC offset which doesn't change the "effective" capacitance. Or a variable voltage depending on the capacitor voltage (generally a*Vcap). Miller and similar effects are observed only in the second case.
 
Re: RC settling and the miller effect

Say now C is connected between vout and a voltage > ground. By virtue of 1 above, would this not make C appear
smaller and hence reduce the rise time over the first case?

Of course not, your capacitor will charge to a lower voltage than the one when is connected directly to ground, time is not influenced.
Likewise, if I connect C between vout and a voltage < grount. By virtue of 1 above, would this not make C appear
larger and hence increase the rise time over the first case?

Of course not, capacitor will charge to a higher voltage than the one when is connected directly to ground, time is not influenced.

So.. charge time of a capacitor is only dependent on R and C (C by it's physical construction) and the settling time is 3 times the time constant.
 
Last edited:
Re: RC settling and the miller effect

Miller effect works when both the ends of cap are connected to ac.
 
Re: RC settling and the miller effect

Thanks guys. I see things clearer now. With the settling case I am looking at a DC offset as the voltage on one side of the cap is clamped to a reference value
where as for the miller effect the voltages on both sides are varying giving rise to a varying effective capacitance. Cheers.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top