Feedback loop calculation for eight bucks in parallel

Hello The attached is a power supply involving eight current mode (CCM) bucks all in parallel, driving into the same load.

Its easy to get the Feedback loop bode plots (& calculate gain and phase margin and crossover) for one buck supplying into one load, but how is it done for eight in parallel?

Vin=28v
vout = 1v5
iout = 136.8A total
Each buck switches at 200khz and they are all interleave phased.
All their transconductance error amplifier outputs are connected together.
There is one output voltage feedback divider going into the "FB" pin of each LTC3892 Buck controller (FB pin is the error amplifier inverting input)

LTspice sim and pdf schem attached.

LTC3892 datasheet
http://cds.linear.com/docs/en/datasheet/38921fb.pdf

There are several ways.

You can control the current that each stage provides: i1+i...+in...+i8=iOut-> in=iOut/8
you just need to implement space state model => dx=Ax+Bu. where x must be x=[il1, vc1,.....il8, vc8].

Same way is applicable to voltage control.

thanks, i assume you are aware that all the error amplifier outputs of the above eight controllers are tied together, and the output voltage is the same node for each buck..therefore, it is essentially just a single SMPS.

treez said:

it is essentially just a single SMPS.

Click to expand...

It can be considered as a single buck copied several times. But remember to deal with interleaving!!

Why don't you simply use an analogue current share bus? When correctly implemented it can accommodate as many modules as required and can cope with faulty/failed modules.
The current share loop can be made really slow. It also means you don't have to connect any sensitive parts of the error amplifier to the outside world.
Unitrode have an app note about it. I've used the concept a few times on designs and it works really well.

Why don't you simply use an analogue current share bus?

Click to expand...

thanks but its too many extra components, the schem in post 1 is the easiest way as there's no extra components to give sharing...all you do is tie the error amp outputs together.

- - - Updated - - -

It can be considered as a single buck copied several times. But remember to deal with interleaving!!

Click to expand...

Thanks but as you know, the interleaving is nothing special, and doesnt make it "more_then_one_SMPS".....i mean, as you well know, a Full Bridge SMPS is just two effectively two two-transistor-forward converters running interleaved...but no-one would call a Full Bridge SMPS "Two SMPS's".
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The point is, as the top post schematic shows, the eight error amplifier outputs are all tied together, so its just one SMPS, but how does the error amplifier small signal transfer function change?, -bearing in mind that there are eight transconductance error amplifiers all acting effectively as one single error amplifier.

Are these PSU's in separate enclosures? If not then it's effectively one PSU as the above post suggests and no current sharing circuitry is required.
If they are in separate enclosures then connecting any part of one controller to another is problematic due to differences in ground potential and noise.
As far as active current sharing is concerned, it requires two op-amps and a few resistors and caps.
Dick

They're all on the same PCB, not separate enclosures.

If interleaving is correct implemented, may use this schematic, with same FB signal to all IC. Sure, each FB must be routed as close to coresponding output (even all are in parallel).
Need to add output capacitors.
Maybe a small inductor after FB point, on each leg, will reduce any circulating current in case of small error/delay in gates signals.

Basically the question is asking what is the transconductance (gm) of n transconductance error amplifiers when they have the same inputs and their outputs are tied together. I believe it is n * gm. Do you agree?

Yes, I agree for n*gm relation but I think a real interleaving (at control level also) disable n-1 amplifiers for time when only one converter is working.
I'm not sure if IC support such disable function or with other words, to enable entire loop accordingly PLLIN external clock signal.

Thanks, such disabling might be nice, but to be honest, we're not bothered about not having that.

The key question has not been answered: suppose one of the "bucks" fails, how the output is affected? What happens when the load is close to the fully rated value?

it depends how it fails...but it may not necessarily do much, other than mean the overall power supply can only deliver 7/8th's of max load. If load is close to full rated value thats no problem.
LTspice sim in top post shows it.