Question about MOS capacitor

Hi everyone,
I wanted to ask you about the graph attached here:



It is from my professor's slides, but I can't find the book from where he took it and I don't think he commented it since I didn't write anything on my copybook.
The question is: I don't really understand the reason why the accumulation area is considered as "bad cap area". The thing I came up with is about electron/hole comparison, which is, in accumulation, since the value of Vgs is negative, the mechanism for capacitance is based on holes accumulated under the gate electrode which "don't really exist", so they aren't reliable for some reason. Just speculating here. I would be glad if someone could explain this for me, since I couldn't find anything similar elsewhere.

Plenty of slides out there:
**broken link removed**
https://homepages.rpi.edu/~sawyes/Models_review.pdf
https://www.eecs.berkeley.edu/~hu/Chenming-Hu_ch5.pdf

BR
Lukas

Thanks Lukas, helpful as usual
I have found an explanation directly from the book from where the picture was taken, I will copy it here so it could be useful for someone else:

"This figure can be misleading. It may appear that we can operate the MOSFET in accumulation if we need a good capacitor. Remembering that when the MOSFET is in accumulation region the majority of the capacitance to ground, Cgb, runs through the large parasitic resistance of the substrare, we see that to operate the MOSFET in this region we need plentiful substrate connections around the gate oxide (to reduce this parasitic substrate resistance). It's preferable to operate the MOSFET in strong inversion when we need a capacitor.

Accumulation, if it's used / implemented properly, can be
a better cap area than inversion. But if you want to use
a standard MOS, your bottom plate contact is not the
S/D but the body tie (tap) which in many kits is left as
almost an afterthought, placed as sparsely as the rules
allow. If you made a "depletion MOS" (like, N+ active in
Nwell) then its accumulation would be a good place and
you'd get robust bottom plate connectivity / higher net
Q.

I have seen many such MOS caps in the processes I've
used. But in vanilla digital CMOS, you may not be given
this PCell or extract rules or model files fitted to the
construction. Just what hand have you been dealt?

Uhm, this was just a random pic on my professor's slides. He didn't comment it at all as far as I remember (not a really advanced course) but I was curious. Do you have any reference for what you posted above?