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want tool regarding the project - vhdl to verilog tool

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supriya123

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sir i want VHDL to VERILOG tool
 

what is the procedure to translate code using this tool. i could not option like translate
 

Hi,

You wants to know how tool is translating or you want to use the tool?

Amit
 

Sorry, in my dictionary there is no such phrase called 'spoon-feeding'!
Amit Kumar has already done some work for you.

Use google search and read carefully the search results is all I can suggest to you.
 

hii
i want how tool is working(like language translation steps)
 

VHDL if =>tool translates=> Verilog if

VHDL AND ==> Verilog &

etc...

these tools generally just perform some sort of lexical substitution and that is why they usually screw up to some extent. My preference hand convert or just leave it as is and run mixed mode simulations.
 

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