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Shift register simulation

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MSAKARIM

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When i simulated a 4-bit serial shift register at Xillinx ISE 13.2 program, i get these wave forms. The problem is that all 4 bits are changed at the same time (no Shifting was happen ). I need to know the problem is in the code or the simulator ?
Code:
Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
    entity SR is
        port ( clk,rst,d : in std_logic;
            q:out std_logic_vector(3 downto 0));
        end SR;
            architecture SR of SR is
                signal qs:std_logic_vector(3 downto 0);
                begin
                    process(clk,rst)
                        begin
                            if rst='1' then qs<="0000";
                            elsif clk'event and clk='1' then 
                            qs(3)<=d;
                            qs(2 downto 0)<=qs(3 downto 1);
                        end if;
                    end process;
                    q<=qs;
    end SR;


Untitled.png

Untitled2.png
 

Your waveforms don't show the transition of d. It just shows all at 1 or all at 0.

Where is your test bench code?
 
andre_teprom said:
Just guessing, but shouldn't the statement q<=qs to be enclosed within the same process ?
Click to expand...
No, it's an assignment statement for pre 2008 connection of a register to an out port.
 
Your rst signal is 0 in the waveform. It should be '1' as per your code
Click to expand...
No, it must be 0 to allow shift register operation. rst would be pulsed to 1 at test start.

There's no actual problem with the code, just that the OP apparently doesn't know how to write a test bench.
 

Hi,

I agree with you FVM. Rst should be 0 at start but after some time it should go to high.
I though waveform has been shared after running the test bench.

Amit
 

Rst should be 0 at start but after some time it should go to high.
Click to expand...
The other way round. It's active high reset, so it must go low before the shift register can start operation.
 

FvM said:
There's no actual problem with the code, just that the OP apparently doesn't know how to write a test bench.
Click to expand...

The OP is showing simulation output at 4us and 5us out from the begining, might be they do have a testbench that is doing something but it's likely doing it near the beginning of the simulation and they are letting it run 400,000 times farther then needed (based on the clock period and the current simulation time).

Also who runs an FPGA simulation with a 10 ps period clock!? What FPGA runs at 100 GHz!? Maybe the OP should learn how to use a simulator by using the venodor's tutorials. Seems like they have the simulator setting for the timescale all messed up.
 
Thanks all for your replies.
I used "force" method in the simulation (right click and force constant), i didn't use test bench method. By the way i simulated the code in Modelsim software and i get what i want. Now i want to know is Xillinx working well only using test bench method ?
 

MSAKARIM said:
Thanks all for your replies.
I used "force" method in the simulation (right click and force constant), i didn't use test bench method. By the way i simulated the code in Modelsim software and i get what i want. Now i want to know is Xillinx working well only using test bench method ?
Click to expand...

If I understand what you are saying by "Xillinx working well only using test bench method". A Xilinx based design (or a design done in any vendors tools) doesn't require a test bench.

Verifying the functionality requires testing, if you test before you implement by running a simulation then using a test bench makes it easier to test complicated designs in a repeatable fashion, which your force method doesn't allow an easy method to do the same.

The simple brute force test bench just assigns inputs to a DUT advances the simulator time, applies new inputs to the DUT, advances time, etc (repeating), until the end of the inputs you want to apply. More advanced test benches will use BFM (bus function models) to stimulate the design , capture DUT outputs, check output results, etc.
 
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