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array assignment in vhdl with signed numbers

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i have to declare an array with numbers like (for eg. 4.344, 2.55, 0.56, 6.33) ...
how to initialize this type of array....

TYPE buf_ary_d IS ARRAY (...????) OF SIGNED(7 DOWNTO 0);

what to write inside bracket
 

Hi,

Inside bracket is the no of element in the array.

ex:
type array_type2 is array (0 to 3) of std_logic_vector(11 downto 0);

Here array is of 4 element with each having 12 bits.

Amit
 
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TYPE buf_ary IS ARRAY(NATURAL RANGE <>) OF UNSIGNED(7 DOWNTO 0);

what does NATURAL RANGE <> mean ?????
 

Natural number range, any subrange of 0 to maxint or maxint downto 0.

You are using this declaration to define a type without specifying the actual range. The range will be specified when referencing the type declaration. Like below:
Code:
TYPE buf_ary IS ARRAY(NATURAL RANGE <>) OF UNSIGNED(7 DOWNTO 0);
SIGNAL buf1 : buf_ary(0 to 5);
SIGNAL buf2 : buf_ary(13 downto 2);
 
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'left and 'right are natual numbers -- the subset of VHDL integers that are not negative. ( n >= 0).

The second part is that decimal values don't have a fully standard representation. VHDL2008 supports fixed point values, were indicies below 0 indicate "fractional bits". for example, bit index 0 represents 1. bit index -1 represents 0.5. index -2 represents 0.25. This is done with sfixed. In previous versions, you would need to use signed, but then keep track of where the fractional bits were.
 

sorry....can you make this explanation simpler.....i did not understand this
 

Numbers like 4.344, 2.55, 0.56, 6.33 are not unsigned. Unsigned can only take integer values.

You can scale the numbers to unsigned by multiplying it with a factor of your choice, preferably 2^N, and rounding to nearest integer. Or read about IEEE fixed point package.
 

TYPE buf_ary_d IS ARRAY (NATURAL RANGE <>) OF SIGNED(7 DOWNTO 0);

will it work for my case ???
 

I overlooked that you want signed, not unsigned. You could e.g. use a scaling factor of 16.
Code:
CONSTANT carray: buf_ary_d(0 to 3) := (
  to_signed(integer(16.0*4.344),8), 
  to_signed(integer(16.0*2.55),8), 
  to_signed(integer(16.0*0.56),8), 
  to_signed(integer(16.0*6.33),8));

- - - Updated - - -

That's without rounding to nearest integer
 

This will only declare an array type that contains 8 bit signed numbers. It doesnt specify what the numbers are.
So using this, you can declare a signal or variable that is an array of signed numbers. Again, it doesnt specify what they are.

- - - Updated - - -

'left and 'right are natual numbers -- the subset of VHDL integers that are not negative. ( n >= 0).

The second part is that decimal values don't have a fully standard representation. VHDL2008 supports fixed point values, were indicies below 0 indicate "fractional bits". for example, bit index 0 represents 1. bit index -1 represents 0.5. index -2 represents 0.25. This is done with sfixed. In previous versions, you would need to use signed, but then keep track of where the fractional bits were.

'left and 'right depend on how the array is defined, and can be integer, character, std_logic or whatever

eg:
Code:
type sl_ar_t is array(std_logic range <>) of natural;
signal my_sl_ar : sl_ar_t('X' to 'H');

my_sl_ar'left = 'X'
my_sl_ar'right = 'H'
my_sl_ar'length = 7

As for VHDL2008 supporting fixed point - the fixed point libraries can almost all be done in VHDL 93. As seen here: www.vhdl.org/fphdl
 

my point on 'left and 'right was a response to "what is natural range <>". I had started the response before your reply to the same question.

(also, you don't need to anchor to 0 on either side)
 

i have to declare an array with numbers like (for eg. 4.344, 2.55, 0.56, 6.33) ...
how to initialize this type of array....

TYPE buf_ary_d IS ARRAY (...????) OF SIGNED(7 DOWNTO 0);

what to write inside bracket

You cann't use numbers with type "real" for synthesys, only in testbench.
 

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