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Verilog assign &

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shaiko

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Hello,

What does this code do?
assign y= & x;
 

'&' is doing a bitwise and operation. i.e. all bits of signal 'x' will be anded with each other and resultant value would be assigned to Y.
 
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    shaiko

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LRM 11.4.9 Reduction operators
Click to expand...
I knew what '&'
What I wasn't familiar with is the single line statement.
 

Assignment operations are mostly single line, isn't it?
 

Sorry, I meant "single argument" - not "single line".
In VHDL unary operators weren't possible before 2008, I didn't know Verilog supports it.
 

Verilog has always supported this unary reduction operator, even my book from '93 (pre-IEEE standardization '95) shows it. VHDL has been slowly copying stuff from Verilog over the years.
 
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