OTA error amplifier in LDO

I had some questions in LDO design when it comes to the error amplifier (EA)

1) Why is it advantageous to use OTAs when designing the error amplifier in LDOs?
I know that we utilize OTA when we are driving small capacitive loads and voltage amplifiers when driving high impedance loads. Since the output of the EA is connected to the gate of the pass transistor device, is an OTA a better option?

2) Is the pass device of LDO always operated in the linear region? I read in a Masters thesis that it is sometimes operated in the saturation region. Is this right?

yes you can place pass transistor in linear . if load current is very high then it is very difficult to place pass transistor in saturation.As long as gain is there in loop it is ok to place pass transistor to keep in triode. It has its effects on stability and PSRR

tenso said:

I had some questions in LDO design when it comes to the error amplifier (EA)

1) Why is it advantageous to use OTAs when designing the error amplifier in LDOs?
I know that we utilize OTA when we are driving small capacitive loads and voltage amplifiers when driving high impedance loads. Since the output of the EA is connected to the gate of the pass transistor device, is an OTA a better option?

Click to expand...

Your question (1) contains a statement (OTAs are advantageous). Is it really true that OTAs are better than opamps?
More than that, OTAs current output connected to the GATE of the pass transistor?

LvW said:

Your question (1) contains a statement (OTAs are advantageous). Is it really true that OTAs are better than opamps?
More than that, OTAs current output connected to the GATE of the pass transistor?

Click to expand...

I should have rephrased my question. Are OTAs better than opamps?
If I am not mistaken, the millikan paper for example uses an OTA for the EA.

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arya.jagadeesh said:

yes you can place pass transistor in linear . if load current is very high then it is very difficult to place pass transistor in saturation.As long as gain is there in loop it is ok to place pass transistor to keep in triode. It has its effects on stability and PSRR

Click to expand...

For an LDO where you would want your quiescent current greater than load current, which mode would you want the pass device to be in? I was under the impression that the pass device was used in the linear region as a resisitor because a linear regulator is like a voltage divider circuit.

OTAs are simple, easy to compensate (shunt C on output)
and easy to slap around with their current limited output
(e.g. soft start, current limit functions). Their gain tanks
with any resistive load, but internal to a CMOS IC there
may be none (just C pretty much).

LDOs operate the pass FET in linear region -when low
supply headroom- but this is not to be assumed - you
have to design for the low line, high load corner (the
LDO case) but also its opposite (high line, low / no
load) and there you may well be in saturation. The
need to swing across that space is probably the biggest
design challenge, especially with regard to compensation
and step-load response, with a highly variable final stage
gain thrown in for good measure.

dick_freebird said:

OTAs are simple, easy to compensate (shunt C on output)
and easy to slap around with their current limited output
(e.g. soft start, current limit functions). Their gain tanks
with any resistive load, but internal to a CMOS IC there
may be none (just C pretty much).

Click to expand...

yeah, thanks for the reply. Your answer helps a lot. I guess the reason why I saw a lot of papers dealing with on chip capacitor LDOs having OTAs as the error amplifier, is because they are easier to compensate.

Just one more question, looking into the gate of the pass transistor, is the load more resistive or capacitive? if it is more resistive, then would you need a buffer stage between the OTA and pass device?

dick_freebird said:

LDOs operate the pass FET in linear region -when low
supply headroom- but this is not to be assumed - you
have to design for the low line, high load corner (the
LDO case) but also its opposite (high line, low / no
load) and there you may well be in saturation. The
need to swing across that space is probably the biggest
design challenge, especially with regard to compensation
and step-load response, with a highly variable final stage
gain thrown in for good measure.

Click to expand...

you mention different corner cases for a linear regulator and that operating mode of the pass device may vary according to these corners. What are these corner cases and is there a resource online ( textbook, article, paper etc.) which talks about this in more detail?

Thanks for the help.

tenso said:

I guess the reason why I saw a lot of papers dealing with on chip capacitor LDOs having OTAs as the error amplifier, is because they are easier to compensate.

Click to expand...

I rather think, that - as far as ICs are concerned - the preferred solutions are OTAs because they need less area if compared with voltage opamps (circuitry for opamps is more demanding).
That´s the primary reason.

Please consider that the slewrate at the gate of your pass device (as its going to have a large area) is an important task. Specially if your are going to design a LDO that uses an onchip capacitor you need enough bandwidth and current to regulate as fast as possible. Therefore additional adoptive feedbackpaths to the gate of the passdevice can be added to increase slewing.

BR
Lukas

LvW said:

I rather think, that - as far as ICs are concerned - the preferred solutions are OTAs because they need less area if compared with voltage opamps (circuitry for opamps is more demanding).
That´s the primary reason.

Click to expand...

the additional circuitry and space is taken up by the output buffer stage, right?