[PIC] Proteus presenting Stack underflow [STKUNF sets, zero returned] when compiling

/* 
 * File:   main.c
 * Author: IBRAHIM LABS
 * EMAIL:  Ibrahimlabs@gmail.com
 *
 * Website: http://www.ibrahimlabs.com/
 *
 * Created on March 16, 2014, 8:05 PM
 */
//#include <pic18f46k22>
#include <xc.h>
#define _XTAL_FREQ  1000000UL      //  10MHz

// CONFIG
// CONFIG1H
#pragma config FOSC = INTIO7    // Oscillator Selection bits (Internal oscillator block, CLKOUT function on OSC2)
#pragma config PLLCFG = OFF     // 4X PLL Enable (Oscillator used directly)
#pragma config PRICLKEN = OFF   // Primary clock enable bit (Primary clock can be disabled by software)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRTEN = OFF     // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
#pragma config CCP3MX = PORTB5  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
#pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTD2   // ECCP2 B output mux bit (P2B is on RD2)
#pragma config MCLRE = EXTMCLR  // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
#pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)

/*
 * 
 */

#define G1 PORTBbits.RB0
#define Y1 PORTBbits.RB1
#define R1 PORTBbits.RB2

#define G2 PORTBbits.RB3
#define Y2 PORTBbits.RB4
#define R2 PORTBbits.RB5

#define G3 PORTCbits.RC0
#define Y3 PORTCbits.RC1
#define R3 PORTCbits.RC2

#define G4 PORTCbits.RC3
#define Y4 PORTCbits.RC4
#define R4 PORTCbits.RC5

#define start PORTAbits.RA4
/*void delay_100ms(unsigned char n)
{
    
}*/

int main() {
    
    while(1)
    {
            G1 = 1;
            R2 = 1;
            R3 = 1;
            R4 = 1;
            
            G2, G3, G4, Y1, Y2, Y3, Y4, R1 = 0;
            
            __delay_ms(100);
            
            Y1 = 1;
            Y2 = 1;
            R3 = 1;
            R4 = 1;
            
            G2, G3, G4, G1, R2, Y3, Y4, R1 = 0;
            
            __delay_ms(100);
            
            G2 = 1;
            R1 = 1;
            R3 = 1;
            R4 = 1;
            
            G1, G3, G4, Y1, Y2, Y3, Y4, R2 = 0;
            
            __delay_ms(100);
            
            Y3 = 1;
            Y2 = 1;
            R1 = 1;
            R4 = 1;
            
            G2, G3, G4, G1, Y1, R3, Y4, R2 = 0;
            
            __delay_ms(100);
            
            G3 = 1;
            R2 = 1;
            R1 = 1;
            R4 = 1;
            
            G2, G1, G4, Y1, Y2, Y3, Y4, R3 = 0;
            
            __delay_ms(100);
            
            Y3 = 1;
            Y4 = 1;
            R1 = 1;
            R2 = 1;
            
            G2, G3, G4, G1, Y2, Y1, R3, R4 = 0;
            
            __delay_ms(100);
            
            G4 = 1;
            R2 = 1;
            R3 = 1;
            R1 = 1;
            
            G2, G3, G1, Y1, Y2, Y3, Y4, R4 = 0;
            
            __delay_ms(100);
            
            Y1 = 1;
            Y4 = 1;
            R3 = 1;
            R2 = 1;
            
            G2, G3, G4, G1, Y2, Y3, R4, R1 = 0;
            
            __delay_ms(100);
    
    }
    
    return 0;
}

PORTXbits.RXY

LATXbits.LATXY