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FPGA RS232 Communication

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Kolnad

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Hello, I am doing some experiments on FPGA Spartan 6.
The experiment is, - Based on the input signal (named "trigger_to_tx"), uart has to transmit the string "Hello" to PC and one LED has to glow (named "tx_done) after the transmission. I have written the Verilog code for this experiment and attached below. For this code how to add input trigger signal and I am unable to see transmission completion in LED.

Code: 
module Top_module(
	input wire clk,   // System clock
   input wire rst,
   input wire trigger_tx,	
   output wire tx,	
	output [39:0]string_to_tx,
	output tx_done
                );

/// Data to Transmit ///
assign string_to_tx="Hello";

uart_tx_fsm fsm0(.clk(clk),
					.rst(rst),
					/*.trigger_tx(trigger_tx),*/
					.tx(tx),
					.string_to_tx(string_to_tx),
					.tx_complete(tx_complete)
					);

assign tx_done=(tx_complete)? 1:0;

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module uart_tx_fsm(
    input wire clk,   //-- System clock
      input wire rst,  //-- Reset (active low)
      output wire tx,    //-- Serial data output
		input [39:0]string_to_tx,
		output tx_complete
                  );

     //Connecting wires
wire ready;
reg start = 0;
reg [7:0] tx_data;

reg tx_done;
parameter BAUDRATE = 1041;

uart_tx TX0 (
    .clk(clk),
    .rst(~rst),
    .tx_data(tx_data),
    .start(start),
    .tx(tx),
    .ready(ready)
);

// Multiplexer with the 8-character string to transmit
always @*
  case (char_count)
    3'd0: tx_data <= string_to_tx[39:32];
    3'd1: tx_data <= string_to_tx[31:24];
    3'd2: tx_data <= string_to_tx[23:16];
    3'd3: tx_data <= string_to_tx[15:8];
    3'd4: tx_data <= string_to_tx[7:0];
	 3'd5: tx_data <= 8'hd;   // Enter
	 default: tx_data <= 8'h20;  //Space
  endcase

// Characters counter
// It only counts when the cena control signal is enabled
reg [2:0] char_count;
reg cena;                // Counter enable

always @(posedge clk)
  if (rst)
    char_count = 0;
  else if (cena)
    char_count = char_count + 1;

                // CONTROLLER

localparam INI = 0;
localparam TXCAR = 1;
localparam NEXTCAR = 2;
localparam STOP = 3;

  // fsm state
reg [1:0] state;
reg [1:0] next_state;

   // Transition between states
always @(posedge clk) begin
  if (rst)
    state <= INI;
  else
    state <= next_state;
end

        // Control signal generation and next states
always @(*) 
  begin
  next_state = state;
  start = 0;
  cena = 0;

  case (state)
     // Initial state. Start the trasmission
    INI: begin
      start = 1;
      next_state = TXCAR;
    end

    // Wait until one car is transmitted
    TXCAR: begin
      if (ready)
        next_state = NEXTCAR;
    end

    // Increment the character counter
    // Finish when it is the last character
    NEXTCAR: begin
      cena = 1;
      if (char_count == 3'd5)
		  begin
        next_state = STOP;
		  end
      else
        next_state = INI;
    end

  endcase
end

assign tx_complete= (char_count==3'd5)? 1:0;

endmodule
 
Last edited by a moderator:

start with debugging your state machine, it doesn't increment to the next character, and it's just the beginning of a UART transmitter.

If you've done that, you will probably know by then how to inject your input trigger.
 
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    K

    Kolnad

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lucbra said:
start with debugging your state machine, it doesn't increment to the next character, and it's just the beginning of a UART transmitter.
Click to expand...

Here I corrected the code and it is transmitting string "Hello" without any triggering signal.

Code: 
module Top_one(
	input wire clk,   //-- System clock
   input wire rst,	
   output wire tx,	//-- Serial data output
	output [39:0]string_to_tx
                );

/// Data to Transmit ///
assign string_to_tx="Hello";

uart_tx_fsm fsm0(.clk(clk),
					.rst(rst),
					.tx(tx),
					.string_to_tx(string_to_tx)
					);

endmodule

///////////////////////////////////////////////////////////////////////////////////////////

module uart_tx_fsm(
input wire clk,   //-- System clock
      input wire rst,  //-- Reset (active low)
      output wire tx,    //-- Serial data output
		input [39:0]string_to_tx
                  );

     //Connecting wires
wire ready;
reg start = 0;
reg [7:0] tx_data;

reg tx_done;
parameter BAUDRATE = 1041;

uart_tx TX0 (
    .clk(clk),
    .rst(~rst),
    .tx_data(tx_data),
    .start(start),
    .tx(tx),
    .ready(ready)
);

// Multiplexer with the 8-character string to transmit
always @*
  case (char_count)
    3'd0: tx_data <= string_to_tx[39:32];
    3'd1: tx_data <= string_to_tx[31:24];
    3'd2: tx_data <= string_to_tx[23:16];
    3'd3: tx_data <= string_to_tx[15:8];
    3'd4: tx_data <= string_to_tx[7:0];
	 3'd5: tx_data <= 8'hd;   // Enter
	 default: tx_data <= 8'h20;  //Space
  endcase

// Characters counter
// It only counts when the cena control signal is enabled
reg [2:0] char_count;
reg cena;                // Counter enable

always @(posedge clk)
  if (rst)
    char_count = 0;
  else if (cena)
    char_count = char_count + 1;

                // CONTROLLER

localparam INI = 0;
localparam TXCAR = 1;
localparam NEXTCAR = 2;
localparam STOP = 3;

  // fsm state
reg [1:0] state;
reg [1:0] next_state;

   // Transition between states
always @(posedge clk) begin
  if (rst)
    state <= INI;
  else
    state <= next_state;
end

        // Control signal generation and next states
always @(*) 
  begin
  next_state = state;
  start = 0;
  cena = 0;

  case (state)
     // Initial state. Start the trasmission
    INI: begin
      start = 1;
      next_state = TXCAR;
    end

    // Wait until one car is transmitted
    TXCAR: begin
      if (ready)
        next_state = NEXTCAR;
    end

    // Increment the character counter
    // Finish when it is the last character
    NEXTCAR: begin
      cena = 1;
      if (char_count == 3'd5)
		  begin
        next_state = STOP;
		  end
      else
        next_state = INI;
    end

  endcase
end

endmodule
 

There's apparently no change expect omitting the trigger and complete signal. So if it outputs a string now (I guess once after reset), it should have done before.

Anyway, what's the problem now?
 

In my experiment, I wanted to include one output signal/flag It should set when transmission completes. Because, I am instantiating one more separate module based on this completion signal. In my program, where can i add that output completion signal?
 

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