Use an FPGA board for outputting parallel bits (parallel 20 bits ) at 100MSPS?

Hi all,

I have a very straightforward requirement:

I need to test my own chip (ASIC).
1st step: Load data from my computer to a RAM. The data width is at most 32 bits. This process does not need to be very fast.
2nd step: Read the data sequentially from the memory and give the data to my chip, which takes in 32bits in parallel. The data rate has to be at least 100MSPS. And I want to be able to control the data rate (by programming the FPGA?)

I would like to know if this is achievable using VC707 evaluation board or other lower end FPGA evaluation board.

I browsed through VC707's user guide and schematic. VC707 Evaluation Board has a DDR3 (Module density: 1GB, 128 MegX64, Module Bandwidth 12.8GB/s, Memory Clock/Data Rate 1.25ns/1600 MT/s) and FMC HPC1/HPC2 Connectors.

Could you please give me some guidelines on how to do this? I have some vague ideas that I may need a memory controller. But it's not very clear if that is the correct path to go.

This is VC707 Evaluation Board's diagram:


The schematic of VC707 can be downloaded from https://secure.xilinx.com/webreg/cl...c707_Schematic_xtp135_rev1_0.pdf&languageID=1

The user guide of VC707 can be downloaded from https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf

Thank you very much!

from your own chip you will know what interface standard it expects (I hope) and DDR3 has a well defined electrical interface well above 100Mbps. Even if you don't use DDR3, Virtex7 has I/O that achieves higher bit rates then 100Mbps.

BTW : A data rate of 100MSPS doesn't make any sense

Thank you very much for the reply.
I haven't decide the interface standard of my chip yet, because it'll depend on the test equipment. I'm exploring the possibilities. If I use a signal generator, I'll have one type of interface on my ASIC. If I use some FPGA evaluation board, I'll have other type of interface on the ASIC.

I would like to minimize the complexity on the ASIC, which will take in 32 bits in parallel. I don't want to have a memory controller on the ASIC and read the external RAM directly. Instead, I would like to read the RAM using an FPGA, which is easier to program and memory interafce module are readily available, and use the FPGA to send the data to my ASIC. On the ASIC, I'll have 32 DFFs clocked at minimally 100 MHz to latch the input. This is what I meant by 100 Mega Samples per Second. It's not 100 Mega Bits per Second.

lucbra said:

from your own chip you will know what interface standard it expects (I hope) and DDR3 has a well defined electrical interface well above 100Mbps. Even if you don't use DDR3, Virtex7 has I/O that achieves higher bit rates then 100Mbps.

BTW : A data rate of 100MSPS doesn't make any sense

Click to expand...

If all you are doing is shuffling data around, usually the simplest transfer method is clock, data, and valid. Whether or not it's LVDS or single ended depends on things like number of pins you can afford to use, signal integrity, EMI, etc.