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Verilog code statement: #

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Re: Verilog code statement

shaiko said:
In a simulation enviroment - it'll assign d to q after 10 simulation ticks.
Or so I think...
Click to expand...

Do mean by after 10 clock.

Code Verilog - [expand]
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module dff8(q,d,clk);
   input [7:0]d;
    input clk;
    output  [7:0] q;
/*     always@(posedge clk) 
    begin*/
assign q= #10 d;
   /* end*/
endmodule


What this module is doing?
 
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Re: Verilog code statement

It assings Q after 10 `timescale units.

For a `timescale of 1ns / 1ps, Q will be assigned after 10 ns.
1ps is the smallest time precision possible in the simulation.
 
Re: Verilog code statement

It assings Q after 10 `timescale units
Click to expand...
What if the "clk" signal that triggers the always block is faster than 10 timescales ?
Will the assignment ever take effect?
 

Re: Verilog code statement

The intra-assignment delay should also work with delay > schedule period. The RHS is evaluated immediately, the LHS assigned after the delay, creating a transport delay.

But there's no valid clock event in the above example.
 
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Re: Verilog code statement

The RHS is evaluated immediately, the LHS assigned after the delay, creating a transport delay.
Click to expand...
As far as I understand - in VHDL one a process is entered (per sensitivity list) and a signal assignment is scheduled - any old scheduled assignments are overridden. This is UNLESS the "transport" keyword is used.

Are you saying that in Verilog all delays are transported by default?
 

Re: Verilog code statement

The behavior isn't explicitly stated in the Verilog LRM, but I believe the intra-assignment delay syntax is the Verilog equivalent to VHDL transport delay.
 
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