[moved] telemetry circuit design help requested

We have a need to a circuit that can accept a data and clock signal at up to 12 megabits/second and make the data available to ingest by a processor. I strongly suspect that this has been done a few times. We also need to build this in as an embedded system, no memory devices other than RAM and the code burned into ROM. My first thought is to use an ARM (or something similar) on a prototype board such as the ones that various companies sell to demonstrate their CPU. We would then connect a programmable IC to clock that data in and let the processor grab it, maybe 16 bits at a time.
I can and do write code to extract what we need from the stream, but have done nothing as far as the hardware to translate from a serial bit stream into something the CPU can handle.
Where might I find the documentation I need on doing this. Have you any suggestions?

Re: telemetry circuit design help requested

If I have understood your requirement correctly....

Have you thought of using an FPGA to do this work?
If yes, you may explore Xilinx 7 series FPGAs, where it is possible to embed soft processor core/s and develop custom logic around it (e.g. - connecting a peripheral hardware from which you can stream in the data) within a single die.
There you will have the possibility of programming either a MicroBlaze or ARM Cortex (depending on the FPGA development board) which have sufficiently large Block-RAM memories as the Inst. and Data memories.

If you want to explore the FPGA path, then please post further questions in the 'PLD, SPLD, GAL, CPLD, FPGA Design' section. This is the ASIC section.

If your plan is to have an embedded system with both programmable logic and an ARM. I suggest you look at the ZYNQ family from Xilinx. It has a hard IP ARM Cortex A9 embedded in the chip, along with programmable logic fabric.

The 12 Mbps isn't all that fast and you can do any preprocessing of the serial data (serial-to-parallel conversion, header parsing, etc) in the programmable logic fabric. Leaving the ARM to do all the complicated decision making.

If your programmable logic is not too big, you can take a look on the PSOC4 MCU from Cypress.

These are the answers I need. I am following up and thank you very much.

I am discovering the capabilities that can be had and used. I am not experienced in this at all. Where should I look for an engineer or engineering services that can build the device I need? This is NOT a rush project. By April we need to determine how feasible this is and a ball park cost and time to complete.

Tetik said:

If your programmable logic is not too big, you can take a look on the PSOC4 MCU from Cypress.

Click to expand...

Cypress PSoC is in fact a very interesting approach, but I fear that will not be able to deal with data stream with 12 megabits/second rate. With some soft core as suggested above perhaps will have a better flexibility to meet to the design requirements.

bkelly said:

I am not experienced in this at all. Where should I look for an engineer or engineering services that can build the device I need? This is NOT a rush project. By April we need to determine how feasible this is and a ball park cost and time to complete.

Click to expand...

bkelly said:

Where should I look for an engineer or engineering services that can build the device I need? This is NOT a rush project. By April we need to determine how feasible this is and a ball park cost and time to complete.

Click to expand...

I can't answer the 1st part of you question, but coming to the second part, if you choose to go the Xilinx FPGA way, one needs to use Vivado suite. Now there are two design approaches to build your proof-of-concept design with Vivado- working in project/GUI mode or batch/TCL mode.

The project/GUI mode is recommended for beginners. There are a lot of free video tutorials out there to get started (of course all specs and docs docs exist apart from the Xilinx Forums). But all this rides on the assumption that the user has basic understanding of digital hardware design concepts, is familiar with one RTL HDL (VHDL or Verilog) and is aware of the FPGA design flow (ASIC flow would also do).

If what I have mentioned above is true, then with an optimistic estimate, a month should be sufficient (I may be wrong in this estimation) in coming up with the proof-of-concept working design. Engineers experienced with FPGA design will take lesser time for this task.

If you want to minimize the hardware cost, I think a DSP is the best solution. They normally have built-in serial ports that can take an external clock, and 12 Mbit/s is not much.
Maybe the DSP also could handle the "application" to give you a one-chip solution for the whole unit.
If you only want to use it as a serial-to parallel interface for another processor, that is also OK. I am not up to date, but a long time ago I did similar things with TI's TMS320C54XX family. They have a very nice parallel host interface (HPI) so another processor can access the internal memory areas. It is very easy to use the DSP internal RAM as a FIFO. The DSP would read the data from the serial port, write it to a circular RAM buffer and update a write pointer. The "host" processor would read directly from the DSP RAM buffer via the HPI interface and update a read pointer.
I expect the price for such a DSP to be less than $5 even in small quantities.

The software for the DSP can be loaded into the internal RAM via the HPI.

reply to ads-ee
I followed the link to the ZYNQ pdf. I knew there was some pretty awesome stuff out there along this line but had not looked recently.
Wow. There are some really awesome chips and configuration files available.
Now I need to pick one, or better, find the right experienced engineer and we will pick one together.
Thank you for your time.