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Regarding PS UART and PL UART difference

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Sunayana Chakradhar

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Hello,

I need to design 2 UARTs on PS of Zynq and 1 UART on PL of Zynq. I have 2 questions regarding this.

1. In PS UART, is it sufficient if I only enable UART0 and UART1? Don't I need to write the code for rx, tx and baudgen and the constraints file? What are the files generated with the PS UART?

2. If I need to generate a 3rd UART on the PL, how do I do it? What files do I need to include? like constraints, source file, drivers etc? Kindly clarify this to me.
 

I tried opening the project in the link. It doesn't open in vivado. I want to know what are the requirements of a PS UART versus a PL UART. Please explain.
 

I think there's no special requirement between PS UART and PL UART. Did you try to add 3 UART in your block design?

I strongly suggest to start with an example design and add the 3 UART. The addresses are managed almost automatically and you can find them in the xparamaters.h file generated by Vivado.
 

Sunayana Chakradhar said:
I tried opening the project in the link. It doesn't open in vivado. I want to know what are the requirements of a PS UART versus a PL UART. Please explain.
Click to expand...

Just downloaded the project and it opens just fine for me in Vivado 2015.1
 

Yeah i have 3 uarts in my design. 2 can be enabled by just checking uart 0 and uart 1 in zynq reconfiguration window. The 3rd one needs to coded on the PL. All I want to know is that the uart which i create on the PL needs hdl coding, constraints file to be written on vivado and drivers file to be written on SDK. Dont we need to do all this for PS UART also?
 

You can simply add the axi_uartlite core into your block design. All you need to do is to assign the uart i/o pin in the constraint file. It is the same driver as the internal uart in the zynq processing system and you can access it in the same manner.

uart_example.jpg
 
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