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timing fixes during logic synthesis

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ivlsi

ivlsi

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Hi All,

What problems might be fixed during logic pre-layout synthesis (besides setup violations)?

Thank you
 

Transition violations, pulse width violations, max delay violations
 
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    ivlsi

    ivlsi

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Hi,

DRV's [design rule violations].max cap,max tran,max fanout.
 

As for the min pulse violations, are they relevant for clocks only or for glue logic as well?

- - - Updated - - -

How can I fix the Max Capacitance and Max FanOut violations?
 

hi,

maxcap and max fanout violations can be decreased by inserting buffers and splitting the load.
 
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