How to lower down the Q of LNA input matching?

improving q of lna

The LNA is designed in CMOS at 1.5GHz. When simulated, the matching has a quite high Q factor. That's not good since it is sensitive to the process variabtion. In this case, what should I do to handle this problem or how to lower down the Q factor while maintaining good NF and gain? Thanks.

lna input matching

The LNA topology will affect the Q of the input match. Source inductance degeneration seems to be the best approach.
To lower the Q of the input match, decrease the inductance to capacitance ratio of the matching components.
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lna dissertation german pdf

yolande_yj said:

The LNA is designed in CMOS at 1.5GHz. When simulated, the matching has a quite high Q factor. That's not good since it is sensitive to the process variabtion. In this case, what should I do to handle this problem or how to lower down the Q factor while maintaining good NF and gain? Thanks.

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Hi, please see the following picture, without C3, this CMOS LNA topology is widely used now.
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It is reported [1] that the input Q is defined as:
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It is independent of Ls, which I believe is correct (I have tried to change Ls and got the same Q from the simulation result). Ls compromises the gain to improve the linearlity.
C3 (or Cgs) is the main component that affact Qin. But I don't think it is a good idea to introduce C3 or increase Cgs to lower down the Qin because with the increase of C3 (or Cgs):
1. Noise Figure (NF) increase (increase quite fast when C3 is large);
2. Available gain (Ga) decrease (quite a lot).
3. Qin decrease not so much as you expect while the degradation of NF and Ga could be unacceptable.
When designing LNA, you have the spec such as NF, gain and SWR. I think a better way to improve the immunity of process variation is to try to get a higher gain (not too high to avoid saturate the following block) to get a larger bandwith within which you can meet your gain spec. The following pictures are LNA (@1.575GHz) simulation results with different:
1. Numbers of turns of Ls (NLs);
2. Size of MIM cap C3 (a×a um²)
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I hope they can give you a rough idea.

[1] Floyd, B.: A CMOS Wireless Interconnect System for multigigahertz Clock Distribution. Ph. D. Dissertation, University of Florida, Gainesville, FL, 2001.

Hi CMOSBJT,

Thank you for your elaborated explanation.

Added after 4 hours 42 minutes:

Hi CMOSBJT

I noticed that in the last 4 figures, beside NFmin, there is a NF(2), why NF(2), why not NF(1)? Thanks.

yolande_yj said:

Hi CMOSBJT

I noticed that in the last 4 figures, beside NFmin, there is a NF(2), why NF(2), why not NF(1)? Thanks.

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I also have this question. I have posted a topic about this problem in this forum before. But I got no answer. NF is defined as the noise figure in the nth terminal, thus NF(2) is the NF we get in the 2nd terminal or output port. NF(1) is always "unreasonably" high according to my simulation.

I think one logical explaination is: like what you do in the NF measurement, you put a noise source before the input port of the DUT and measure the NF at the output port (using NM or SA). Similary, we get a desired NF at output port, which is NF(2). The High NF(1) is because the low reverse gain S12.

Since I can not find any explaination about this question, I come out of these "theory" by myself. Please correct me if you know the answer.