High voltage input cascaded buck converter

100 volt 300 watt non isolated power
ltspice asc file.

[change .txt to .asc]

thanks but we need load to be ground referenced. Nice circuit though

My other projects here.
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not English.
But the files (png asc) are universal. I would be happy if you Comments. everybody.

In fact, there is a very good reason to use a Dual cascaded buck converter (as in the schematic below) instead of a single buck stage for the MWD application which is as follows….
Vin = 120-400vdc
Vout = 100vdc
Pout = 300w
Ambient temperature = 170degC

The point is that for MWD applications, the high ambient temperature of 170degC means that “proper” gate drive transformers that have ultra low leakage inductance cannot be made. Therefore, one is stuck with gate drive transformers with relatively high leakage inductance. (This is because “proper” gate drive transformers use bifilar wound primary and secondary coils which are spread evenly round the circumference of the torroid. The bifilar coils have to be glued to the torroid so that they stay in place on the torroid, and don’t bunch up at one part of the circumference of the torroid core. However, such glue cannot be used for hot MWD applications because the glue melts.)
Therefore, for MWD applications, one has to use ETD type ferrite cores (and not torroids) for the gate drive transformer. –The bifilar turns are wound evenly over the ETD bobbin, and then taped in place....this results in more leakage inductance than when a torroid is used.

So anyway, when you are doing a step down SMPS, for MWD, with vin=400V, vout=100v, pout=300W, for MWD applications, you need to do it with a buck converter, and the high side fet gate drive transformer will have much leakage inductance. Therefore, your hi side FET switch-on transition time will be long, due to the unavoidable high leakage inductance in the Gate drive transformer. This is bad because your FET switch-on transition time should not be a large percentage of the overall fet on time. Therefore, in order to make the switching transistion time a smaller percentage of the fet on time, you have to increase the fet on time. –And the way to increase the fet on time is to operate the buck converter as a dual cascaded buck converter, because then your fet duty cycle goes to about 0.5, instead of the 0.25 that you would get with a single buck stage…Thus your fet on time is increased, and your high switching transition time, becomes a smaller proportion of your overall fet on time.

Another reason that the buck must be cascaded for this application is that the switching losses of each of the fets is slightly less, and in fact, the “per FET” dissipation is less than in a single buck stage……this is because the upstream fet of the dual cascaded buck converter has a lower peak current than the fet of the single buck stage, and so less switching loss , and less reverse recovery problem for the diode. Also, the downstream buck of the dual cascaded buck is switching less voltage so has less switching loss…….so it is definite that the individual fets of the dual cadscaded buck converter dissipate less than the individual fet of the single stage buck converter….”so what!” I hear you say……well, here’s what…….when your ambient temperature , and your heatsinks, are at 170degC, then this thing of having a lower “per FET” dissipation is really important..because its really difficult to get heat out of fets when the heatsink is at 170degC. So this thing of having a lower “per FET” dissipation is really important...so that's why a dual cascaded buck is needed instead of a single buck stage.

Schem and ltspice sim of dual cascaded buck attached.

So there are the reasons that a Dual Cascaded Buck Converter is far more advantageous than a Single Stage Buck Converter for this application…do you agree?

Hi, obviously the increased fet on time making the fet switching transition less significant is wide of the mark, but what about the reduced "per FET" dissipation situation with the dual cascaded buck?