how can i reduce the power

Hi,

As a backend designer, how can I reduce the POWER & IR drop? (I don’t want to make any changes in the code.)

Thanks in advance

Rahul

You can use power synthesis to reduce power. And power synthesis you can find at synopsys synthesis tools , but you need the power synthesis license.

Hi stormwolf


Thanks for your suggestion, but problem is, I am using MAGMA.
Can you give me a general idea, not related to any tool.

Thank you

Rahul

power compiler of synopsys will optimize the power consumption, but may change the timing, BTW, you have to verify all aspects of design after optimization.
If you don't want to change the netlist, the only thing that you can do is doing a good floorplanning and reduce the wire length between data dependent blocks as much as possible to reduce IR drops. But I'm not sure that it reduces the power consumption.

There are techniques such as clock gating...which are very effective in reducing power consumption. Also minimize the use of buses as they hog power. Your DFT can get complicated if you use clock gatting.

If you dont wanna change the codes,maybe you will have to refer to the tools to reduce the power.
Here is a document about clock_gating,you may read it and see how the tool is used to reduce power.
Hope it will help you.
I'm also using Magma,there's also tools in Magma to reduce power.

There are a lot of ways to reduce the power dissipation:
(1) the systematic view: of cause, this is not your concern such as different algorithm and different architecture
(2) the circuit/logic design such as clock gating and good FSM coding styles to reduce the transitional rate of the circuit nodes
(3) the performance consideration such as low frequency/low voltage, please see the following equation=∑αcvf*f
(4) the techonological and device view such as dual-threshold devices: the low trheshold devices are applided for the high performace circuits while the high trheshold devices are used for the low performance circuits
(5) the floorplan view such as the global wire length reduction so as to reduce the parasitic resistance and capacitance
(6) the P&R strategy view such as the timing-driven strategy or the area-driven strategy

you can put related logic together to minimize interconnect wire's length,

thus wire capacitance is reduced.

shelkerahul said:

Hi,

As a backend designer, how can I reduce the POWER & IR drop? (I don’t want to make any changes in the code.)

Thanks in advance

Rahul

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