beginner_EDA
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Hi,
This is how a state machine is normally written using process.
What I have not understood here default (before Idle state start). What is default ? What happened in default case? how default case affect output both in transition process and output decoding process?
This is how a state machine is normally written using process.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 type STATES is ( Idle, FIFO_Flush, FIFO_FlushFinish, state1, state2, state3 ); signal State : STATES; signal StateNext : STATES; Prc_StateMem: process(clk, Reset) begin if rising_edge(clk) then if Reset = '1' then State <= Idle; else State <= StateNext; end if; end if; end process Prc_StateMem; Prc_Transition: process(State, input1, input2, input3) begin -- Defaults StateNext <= State; case State is when Idle => if input1 = '1' then StateNext <= FIFO_Flush; end if; -- clean FIFO. when FIFO_Flush => StateNext <= FIFO_FlushFinish; when FIFO_FlushFinish => if input2 = '0' then StateNext <= state1; end if; when state1 => StateNext <= state2; when state2 => StateNext <= state3; when state3 => if input3 = '0' then StateNext <= Idle; end if; when others => StateNext <= Idle; end case; end process Prc_Transition; Prc_Output: process(State, StateNext, input4, constant1, constant2, Tx_FIFO_WrReq) begin -- Defaults Busy <= '1'; FlushFIFO <= '0'; FIFO_WrReq <= Tx_FIFO_WrReq; FIFO_WrData <= input4; case State is when Idle => Busy <= '0'; when FIFO_Flush => FlushFIFO <= '1'; when FIFO_FlushFinish => when state1 => FIFO_WrReq <= '1'; FIFO_WrData <= constant1; when state2 => FIFO_WrReq <= '1'; FIFO_WrData <= constant2; when state3 => FIFO_WrReq <= Tx_FIFO_WrReq; FIFO_WrData <= input4; when others => end case; end process Prc_Output;
What I have not understood here default (before Idle state start). What is default ? What happened in default case? how default case affect output both in transition process and output decoding process?
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