Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
It means that it didn't find the component main1. Make sure that the component main1 is compiled and that you instantiate correctly that component in your testbench.
Your simulation won't work because there component main1 is "empty".
usually happens if there is some mismatched ports in the actual entity declaration and the component declaration. Basically it means the component instance wasn't attached to the rest of the design so you'll definitely have a simulation that doesn't run correctly.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
