[Moved]: splitting up signal paths "logic"

Hi,

I was about to prototype a board for FPGA. Since I'm not entirely shure I may want to do some changes to it, can I split up general purpose IO and a stick of RAM for instance, so that regarding the application I can use one or the other. I was wondering how bad would it be?

Depends on your application and choice of FPGA
https://www.xilinx.com/fpga/index.htm

Whatever you do, don't pour saltwater over it while the power is turned on.

A prototype for what purpose?
Is it a learning project?
Why would you want to "split" things?
What IOs?
And where can I get a "RAM stick"? Don't you need a license for it?!

It's a synthesizer. At least a platform to program some audio.
I'm set up for Altera so I thinking along the lines of a cyclone III, at 72MHz. Retaining the option to have the PLL upsampling it for the memory.

One of the builds I want to start with does not use ram, but I like to have acces to it just in case. So designwise it would be cool to fork this with some GPIO connectors.

But it's all logic, the ram is the most sensitive to static by far. AFAIK you can have it shout the 3.3v across..

So I mean a slotted personal computer stick of ram. Or a slot at first..

So I mean a slotted personal computer stick of ram. Or a slot at first..

Click to expand...

"Sticks" are used to chase away rabid raccoons - never seen them on board.
The technical term is DIMM.
https://en.wikipedia.org/wiki/DIMM
DIMMs used when you need to address large (>2Gb) amount of storage space.
Do you really need it??
It'll make the board layout much more complicated (and expensive).
Instead, you can have a couple of onboard memory chip footprints prepared - solder them when you need.
Regarding the IO's, I suggest buffering and ESD protecting only the ones that lead to the outside world (go to connectors ) - nothing more.

This sounds like an interesting project - but your board design skills require honing.
I suggest you find a good reference design online and learn from it.

I don't understand exactly what you mean by buffering. The outgoing register is acting like a buffer "right"? All I was planning to do is to elaborate the overvolt protection I got on one of my boards (schottky diodes and a resistor).

But seeing your tip it may be redundant if played safe? since its largely inputs on the GPIO, And I can either terminate or pull up the RAM or GPIO on chip.

And youre right, it's actually my first digital computer aided design. Besides from having the software side down. Yust want to make shure given theres a ground and power plane, the solution proposed doesn't corrupt the data going through.

I don't understand exactly what you mean by buffering.

Click to expand...

By buffer - I mean a current driving IC. Put it between any FPGA IO and a connector pin.
This way, if there's a short circuit or any other electrical malfunction - the 0.50$ buffer gets it instead of the impossible to hand solder 50$ FPGA.
https://www.fairchildsemi.com/products/logic/buffers-drivers-transceivers/buffers/NC7SV126.html

But seeing your tip it may be redundant if played safe? since its largely inputs on the GPIO, And I can either terminate or pull up the RAM or GPIO on chip.

Click to expand...

Choose your required external memory size and bandwidth and continue from there. Consult the chosen vendor's datasheet at every step you take.

Regarding termination - if you're not sure about it, I suggest you put a 0ohm resistor in series.

Yust want to make shure given theres a ground and power plane, the solution proposed doesn't corrupt the data going through.

Click to expand...

There're many other things that are important if you want to design your board properly.
An FPGA is probably the most complex digital device one can put on board.

Educate yourself on the following subjects:

1. Decoupling capacitors.
2. Allowable parallel bus length mismatch.
3. Termination resistors.
4. Altera FPGA pin-out documentation (for the Cyclone III).
5. Board stack-up.

Take things slowly.
The less you know now, the more time you'll spend debugging your masterpiece later.